>From d1429f0bef16eb850a4ccc879cdc2212b41da40c Mon Sep 17 00:00:00 2001 From: Avi Kivity Date: Sun, 18 Mar 2012 11:42:00 +0200 Subject: [PATCH] sparc64: trim low-order bits from TLB entry during MMU translation get_physical_address() returns a physical address with random low bits set, which confuses tlb_set_page(). Fix by masking the low-order bits. Signed-off-by: Avi Kivity --- target-sparc/mmu_helper.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c index 11fb9f5..27f7b27 100644 --- a/target-sparc/mmu_helper.c +++ b/target-sparc/mmu_helper.c @@ -491,7 +491,7 @@ static int get_physical_address_data(CPUSPARCState *env, mmu_idx == MMU_USER_SECONDARY_IDX); if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ - *physical = ultrasparc_truncate_physical(address); + *physical = ultrasparc_truncate_physical(address) & TARGET_PAGE_MASK; *prot = PAGE_READ | PAGE_WRITE; return 0; } @@ -610,7 +610,7 @@ static int get_physical_address_code(CPUSPARCState *env, if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) { /* IMMU disabled */ - *physical = ultrasparc_truncate_physical(address); + *physical = ultrasparc_truncate_physical(address) & TARGET_PAGE_MASK; *prot = PAGE_EXEC; return 0; } -- 1.7.9