qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] Question about the block linking limitation


From: Max Filippov
Subject: Re: [Qemu-devel] Question about the block linking limitation
Date: Thu, 12 Apr 2012 01:27:08 +0400

On Thu, Apr 12, 2012 at 1:04 AM, Peter Maydell <address@hidden> wrote:
> On 11 April 2012 22:00, Max Filippov <address@hidden> wrote:
>> 陳韋任 <address@hidden>:
>>>  Doesn't a tb spanning guest pages have above problem? I mean what if the
>>> guest page 2 is changed? In this case, the execution flow jump from tb.a to
>>> tb.b. It seems it may have the same problem as above to me.
>>
>> I agree. I see that only i386 and m68k TBs may cross page boundary.
>> Maybe it is due to the fact that these CPUs can normally have instructions
>> crossing page boundary due to the variable opcode length.
>
> Hmm. ARM can also have instructions spanning a page boundary (32 bit
> Thumb instructions). I wonder if we get this right :-)

Hm, I didn't know that, but I didn't claim that other architectures
cannot do that.

I meant, I've looked at every gen_intermediate_code_internal and all of them
except i386's and m68k's stop translation on a page boundary.

Although there are variations: some (like alpha, mips or PPC) stop translation
exactly on a page boundary, others (like ARM, lm32 or xtensa) stop on
any offset into another page.

-- 
Thanks.
-- Max



reply via email to

[Prev in Thread] Current Thread [Next in Thread]