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[Qemu-devel] [PATCH 29/32] target-arm: Remove c0_cachetype CPUARMState f
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 29/32] target-arm: Remove c0_cachetype CPUARMState field |
Date: |
Sun, 15 Apr 2012 14:46:22 +0100 |
Remove the no-longer-used CPUARMState c0_cachetype field.
Although this was a constant register we had it in our
migration state. Drop this (with resulting version bump)
because for ARM currently we prefer cleaner migration
code and have not stabilised migration format yet.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 3 +--
target-arm/machine.c | 2 --
2 files changed, 1 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index e7cd584..ded0118 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -107,7 +107,6 @@ typedef struct CPUARMState {
/* System control coprocessor (cp15) */
struct {
uint32_t c0_cpuid;
- uint32_t c0_cachetype;
uint32_t c0_cssel; /* Cache size selection. */
uint32_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
@@ -663,7 +662,7 @@ static inline int cp_access_ok(CPUARMState *env,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
-#define CPU_SAVE_VERSION 6
+#define CPU_SAVE_VERSION 7
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-arm/machine.c b/target-arm/machine.c
index f66b8df..a2a75fb 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -21,7 +21,6 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->fiq_regs[i]);
}
qemu_put_be32(f, env->cp15.c0_cpuid);
- qemu_put_be32(f, env->cp15.c0_cachetype);
qemu_put_be32(f, env->cp15.c0_cssel);
qemu_put_be32(f, env->cp15.c1_sys);
qemu_put_be32(f, env->cp15.c1_coproc);
@@ -139,7 +138,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->fiq_regs[i] = qemu_get_be32(f);
}
env->cp15.c0_cpuid = qemu_get_be32(f);
- env->cp15.c0_cachetype = qemu_get_be32(f);
env->cp15.c0_cssel = qemu_get_be32(f);
env->cp15.c1_sys = qemu_get_be32(f);
env->cp15.c1_coproc = qemu_get_be32(f);
--
1.7.1
- [Qemu-devel] [PATCH 00/32] target-arm: refactor copro register implementation, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 06/32] target-arm: Add register_cp_regs_for_features(), Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 10/32] target-arm: Convert TLS registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 01/32] target-arm: initial coprocessor register framework, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 27/32] target-arm: Convert MPIDR, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 25/32] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 26/32] target-arm: Convert cp15 cache ID registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 16/32] target-arm: Convert cp15 crn=13 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 29/32] target-arm: Remove c0_cachetype CPUARMState field,
Peter Maydell <=
- [Qemu-devel] [PATCH 05/32] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 11/32] target-arm: Convert performance monitor registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 04/32] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 23/32] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 31/32] target-arm: Remove remaining old cp15 infrastructure, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 08/32] target-arm: Convert TEECR, TEEHBR to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 15/32] target-arm: Convert cp15 crn=2 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 02/32] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 14/32] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 28/32] target-arm: Convert final ID registers, Peter Maydell, 2012/04/15