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[Qemu-devel] [PATCH 30/32] target-arm: Move block cache ops to new cp15
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 30/32] target-arm: Move block cache ops to new cp15 framework |
Date: |
Sun, 15 Apr 2012 14:46:23 +0100 |
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 13 +++++++++++++
target-arm/translate.c | 7 +------
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ef99d1c..aef2e26 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -815,6 +815,19 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
/* We never have a a block transfer operation in progress */
{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* The cache ops themselves: these all NOP for QEMU */
+ { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
+ .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
+ .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
+ .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
REGINFO_SENTINEL
};
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6f7932f..09e2165 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env,
DisasContext *s, uint32_t insn)
return 1;
if ((insn & (1 << 25)) == 0) {
- if (insn & (1 << 20)) {
- /* mrrc */
- return 1;
- }
- /* mcrr. Used for block cache operations, so implement as no-op. */
- return 0;
+ return 1;
}
if ((insn & (1 << 4)) == 0) {
/* cdp */
--
1.7.1
- [Qemu-devel] [PATCH 05/32] target-arm: Remove old cpu_arm_set_cp_io infrastructure, (continued)
- [Qemu-devel] [PATCH 05/32] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 11/32] target-arm: Convert performance monitor registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 04/32] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 23/32] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 31/32] target-arm: Remove remaining old cp15 infrastructure, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 08/32] target-arm: Convert TEECR, TEEHBR to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 15/32] target-arm: Convert cp15 crn=2 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 02/32] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 14/32] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 28/32] target-arm: Convert final ID registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 30/32] target-arm: Move block cache ops to new cp15 framework,
Peter Maydell <=
- [Qemu-devel] [PATCH 18/32] target-arm: Convert cp15 crn=15 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 03/32] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 32/32] target-arm: Remove ARM_CPUID_* macros, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 12/32] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 13/32] target-arm: Convert cp15 c3 register, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 07/32] target-arm: Convert debug registers to cp_reginfo, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 09/32] target-arm: Convert WFI/barriers special cases to cp_reginfo, Peter Maydell, 2012/04/15
- Re: [Qemu-devel] [PATCH 00/32] target-arm: refactor copro register implementation, Peter Maydell, 2012/04/27