[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 17/32] target-arm: Convert cp15 crn=10 registers
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 17/32] target-arm: Convert cp15 crn=10 registers |
Date: |
Sun, 15 Apr 2012 14:46:10 +0100 |
We RAZ/WI the entire block of crn=10 registers. Note that this
actually covers not just the implementation-defined TLB
lockdown registers but also a number of v7 VMSA memory
attribute registers which we would need to implement to
support TEX remap. We retain the previous QEMU behaviour
in this conversion, though.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 11 +++++------
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 29578be..463ae4f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -111,6 +111,11 @@ static const ARMCPRegInfo cp_reginfo[] = {
{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 =
1,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
.resetvalue = 0, .writefn = contextidr_write },
+ /* ??? This covers not just the impdef TLB lockdown registers but also
+ * some v7VMSA registers relating to TEX remap, so it is overly broad.
+ */
+ { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
+ .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
@@ -1783,9 +1788,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn,
uint32_t val)
goto bad_reg;
}
break;
- case 10: /* MMU TLB lockdown. */
- /* ??? TLB lockdown not implemented. */
- break;
case 12: /* Reserved. */
goto bad_reg;
case 15: /* Implementation specific. */
@@ -2063,9 +2065,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
goto bad_reg;
}
break;
- case 10: /* MMU TLB lockdown. */
- /* ??? TLB lockdown not implemented. */
- return 0;
case 11: /* TCM DMA control. */
case 12: /* Reserved. */
goto bad_reg;
--
1.7.1
- [Qemu-devel] [PATCH 00/32] target-arm: refactor copro register implementation, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 06/32] target-arm: Add register_cp_regs_for_features(), Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 10/32] target-arm: Convert TLS registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 01/32] target-arm: initial coprocessor register framework, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 27/32] target-arm: Convert MPIDR, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 25/32] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 26/32] target-arm: Convert cp15 cache ID registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 22/32] target-arm: Convert cp15 crn=6 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 19/32] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 21/32] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 17/32] target-arm: Convert cp15 crn=10 registers,
Peter Maydell <=
- [Qemu-devel] [PATCH 24/32] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 20/32] target-arm: Convert cp15 VA-PA translation registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 16/32] target-arm: Convert cp15 crn=13 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 29/32] target-arm: Remove c0_cachetype CPUARMState field, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 05/32] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 11/32] target-arm: Convert performance monitor registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 04/32] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 23/32] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 31/32] target-arm: Remove remaining old cp15 infrastructure, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 08/32] target-arm: Convert TEECR, TEEHBR to new scheme, Peter Maydell, 2012/04/15