Re: [Qemu-devel] [PATCH 3/4] Switch from array based resource allocation to list

[Alexey Korolev]

On Thu, Apr 12, 2012 at 03:28:02PM +1200, Alexey Korolev wrote:
>> On 12/04/12 15:15, Kevin O'Connor wrote:
>>> This was also me playing with one of Gerd's patches.  It just makes
>>> the bar read/write code 64bit aware.  It doesn't actually program
>>> them.  The logic to do real 64bit allocations would require list
>>> merging.  Is this something you have looked at?
>> Right. I see what you mean here. Shall I play around with 64bit
>> support on top of these patches?
> If that makes sense, then sure.
>
> -Kevin
Hi Kevin,

Here is the whole series of patches including 64bit support.
I don't send this in a different thread as this continues the previous 
discussion.

To save your time on parsing I've added little descriptions of changes 
comparing to patches you have sent.

[Patches 1-4]
The same as previous patches just comment about bar=-1 is added

[Patch 5]
Track-alignment-explicitly
Almost the same as the previous, just changed priority from r->align to r->sum 
when setting start address of root regions.

I guess there are more chances to fit memory regions if we try place regions 
with higher r->sum like it was before.
Consider default config
#define BUILD_PCIMEM_START       0xe0000000
#define BUILD_PCIMEM_END          0xfec00000 

Image we have 1 pref. mem. region of 128MB. And many small memory regions which 
take rest of available 492MB - 128MB
If we have alignment priority.
PCI pref memory region will start from F000 0000
and
PCI memoryregion will start from 0xe0000000
and do not fit.

If we choose size based priority it will fit.

[Patch 6]
pciinit-bridges-can-have-two-regions-too
Changed as we discussed. Now taking into account ROM regions too.

[Patch 7]
Switch-to-64bit-variable-types.patch
Same as prvious

[Patch 8 ]
New: The pci_region structure is added.
 Move setting of bus base address to pci_region_map_entries.

[Patch 9 ]
New: Add discovery if bridge region is 64bit is capable.

[Patch 10]
New:  Migrate 64bit entries to 64bit pci regions
 if they do not fit in 32bit range. Pci region stats
 are now calculated. Added protection when total size of
 PCI resources is over 4GB.

[Patch 11]
New: This patch solves issues on Windows guests, when 64bit
 BAR's are present. It is also helpful on Linux guests
 when use_crs kernel boot option is set.

0000-cover-letter.patch
Description: Text Data

0001-pciinit-Introduction-of-pci_region_entry-structure.patch
Description: Text Data

0002-pciinit-Move-bus-bar-asignment.patch
Description: Text Data

0003-pciinit-Remove-size-element-from-pci_bus-r-structure.patch
Description: Text Data

0004-pciinit-Use-sorted-order-allocation.patch
Description: Text Data

0005-pciinit-Track-alignment-explicitly.patch
Description: Text Data

0006-pciinit-bridges-can-have-two-regions-too.patch
Description: Text Data

0007-pciinit-Switch-to-64bit-variable-types.patch
Description: Text Data

0008-pciinit-Add-pci_region-structure.patch
Description: Text Data

0009-pciinit-64bit-capability-discovery-for-pci-bridges.patch
Description: Text Data

0010-pciinit-Migrate-64bit-entries-to-64bit-pci-regions.patch
Description: Text Data

0011-Fix-64bit-PCI-issues-on-Windows.patch
Description: Text Data