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[Qemu-devel] [PATCH 07/14] target-arm: Move SCTLR reset value setup to p
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From: |
Peter Maydell |
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Subject: |
[Qemu-devel] [PATCH 07/14] target-arm: Move SCTLR reset value setup to per cpu init fns |
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Date: |
Sat, 21 Apr 2012 19:30:01 +0100 |
Move the reset value of SCTLR to ARMCPU, initialised in
the per-cpu init functions. It can then be reset by a
simple copy, and we can drop the code from cpu_reset_model_id().
Signed-off-by: Peter Maydell <address@hidden>
Acked-by: Andreas Färber <address@hidden>
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 23 +++++++++++++++++++++++
target-arm/helper.c | 13 +------------
3 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index cb9198a..97f7e90 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -74,6 +74,7 @@ typedef struct ARMCPU {
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t ctr;
+ uint32_t reset_sctlr;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 4f19d5c..74a7d20 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -102,6 +102,7 @@ static void arm926_initfn(Object *obj)
cpu->midr = ARM_CPUID_ARM926;
cpu->reset_fpsid = 0x41011090;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
}
static void arm946_initfn(Object *obj)
@@ -111,6 +112,7 @@ static void arm946_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_MPU);
cpu->midr = ARM_CPUID_ARM946;
cpu->ctr = 0x0f004006;
+ cpu->reset_sctlr = 0x00000078;
}
static void arm1026_initfn(Object *obj)
@@ -122,6 +124,7 @@ static void arm1026_initfn(Object *obj)
cpu->midr = ARM_CPUID_ARM1026;
cpu->reset_fpsid = 0x410110a0;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00090078;
}
static void arm1136_r2_initfn(Object *obj)
@@ -134,6 +137,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
}
static void arm1136_initfn(Object *obj)
@@ -147,6 +151,7 @@ static void arm1136_initfn(Object *obj)
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
}
static void arm1176_initfn(Object *obj)
@@ -160,6 +165,7 @@ static void arm1176_initfn(Object *obj)
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
+ cpu->reset_sctlr = 0x00050078;
}
static void arm11mpcore_initfn(Object *obj)
@@ -195,6 +201,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x00011100;
cpu->ctr = 0x82048004;
+ cpu->reset_sctlr = 0x00c50078;
}
static void cortex_a9_initfn(Object *obj)
@@ -215,6 +222,7 @@ static void cortex_a9_initfn(Object *obj)
cpu->mvfr0 = 0x11110222;
cpu->mvfr1 = 0x01111111;
cpu->ctr = 0x80038003;
+ cpu->reset_sctlr = 0x00c50078;
}
static void cortex_a15_initfn(Object *obj)
@@ -233,6 +241,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->mvfr0 = 0x10110222;
cpu->mvfr1 = 0x11111111;
cpu->ctr = 0x8444c004;
+ cpu->reset_sctlr = 0x00c50078;
}
static void ti925t_initfn(Object *obj)
@@ -242,6 +251,7 @@ static void ti925t_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
cpu->midr = ARM_CPUID_TI925T;
cpu->ctr = 0x5109149;
+ cpu->reset_sctlr = 0x00000070;
}
static void sa1100_initfn(Object *obj)
@@ -249,6 +259,7 @@ static void sa1100_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1100;
+ cpu->reset_sctlr = 0x00000070;
}
static void sa1110_initfn(Object *obj)
@@ -256,6 +267,7 @@ static void sa1110_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
cpu->midr = ARM_CPUID_SA1110;
+ cpu->reset_sctlr = 0x00000070;
}
static void pxa250_initfn(Object *obj)
@@ -265,6 +277,7 @@ static void pxa250_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA250;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa255_initfn(Object *obj)
@@ -274,6 +287,7 @@ static void pxa255_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA255;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa260_initfn(Object *obj)
@@ -283,6 +297,7 @@ static void pxa260_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA260;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa261_initfn(Object *obj)
@@ -292,6 +307,7 @@ static void pxa261_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA261;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa262_initfn(Object *obj)
@@ -301,6 +317,7 @@ static void pxa262_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_XSCALE);
cpu->midr = ARM_CPUID_PXA262;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa270a0_initfn(Object *obj)
@@ -311,6 +328,7 @@ static void pxa270a0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A0;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa270a1_initfn(Object *obj)
@@ -321,6 +339,7 @@ static void pxa270a1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_A1;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa270b0_initfn(Object *obj)
@@ -331,6 +350,7 @@ static void pxa270b0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B0;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa270b1_initfn(Object *obj)
@@ -341,6 +361,7 @@ static void pxa270b1_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_B1;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa270c0_initfn(Object *obj)
@@ -351,6 +372,7 @@ static void pxa270c0_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_C0;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void pxa270c5_initfn(Object *obj)
@@ -361,6 +383,7 @@ static void pxa270c5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
cpu->midr = ARM_CPUID_PXA270_C5;
cpu->ctr = 0xd172172;
+ cpu->reset_sctlr = 0x00000078;
}
static void arm_any_initfn(Object *obj)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index a23df14..eab25ca 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -50,13 +50,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
{
switch (id) {
case ARM_CPUID_ARM926:
- env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM946:
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_ARM1026:
- env->cp15.c1_sys = 0x00090078;
break;
case ARM_CPUID_ARM1136:
/* This is the 1136 r1, which is a v6K core */
@@ -71,12 +68,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
*/
memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM1176:
memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
- env->cp15.c1_sys = 0x00050078;
break;
case ARM_CPUID_ARM11MPCORE:
memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -89,7 +84,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA9:
memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -97,7 +91,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXA15:
memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
@@ -106,7 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
- env->cp15.c1_sys = 0x00c50078;
break;
case ARM_CPUID_CORTEXM3:
break;
@@ -114,7 +106,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
break;
case ARM_CPUID_TI915T:
case ARM_CPUID_TI925T:
- env->cp15.c1_sys = 0x00000070;
env->cp15.c15_i_max = 0x000;
env->cp15.c15_i_min = 0xff0;
break;
@@ -124,7 +115,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
case ARM_CPUID_PXA261:
case ARM_CPUID_PXA262:
/* JTAG_ID is ((id << 28) | 0x09265013) */
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_PXA270_A0:
case ARM_CPUID_PXA270_A1:
@@ -134,11 +124,9 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
id)
case ARM_CPUID_PXA270_C5:
/* JTAG_ID is ((id << 28) | 0x09265013) */
env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
- env->cp15.c1_sys = 0x00000078;
break;
case ARM_CPUID_SA1100:
case ARM_CPUID_SA1110:
- env->cp15.c1_sys = 0x00000070;
break;
default:
cpu_abort(env, "Bad CPU ID: %x\n", id);
@@ -173,6 +161,7 @@ void cpu_state_reset(CPUARMState *env)
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
env->cp15.c0_cachetype = cpu->ctr;
+ env->cp15.c1_sys = cpu->reset_sctlr;
#if defined (CONFIG_USER_ONLY)
env->uncached_cpsr = ARM_CPU_MODE_USR;
--
1.7.1
- [Qemu-devel] [PATCH 12/14] target-arm: Move cache ID register setup to cpu specific init fns, (continued)
- [Qemu-devel] [PATCH 12/14] target-arm: Move cache ID register setup to cpu specific init fns, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 05/14] target-arm: Move MVFR* setup to per cpu init fns, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 10/14] target-arm: Move feature register setup to per-CPU init fns, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 09/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 11/14] target-arm: Move OMAP cp15_i_{max, min} reset to cpu_state_reset, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 01/14] target-arm: remind to keep arm features in sync with linux-user/elfload.c, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 03/14] target-arm: Move feature bit settings to CPU init fns, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 02/14] target-arm: Add QOM subclasses for each ARM cpu implementation, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 14/14] target-arm: Move reset handling to arm_cpu_reset, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 08/14] target-arm: Drop JTAG_ID documentation, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 07/14] target-arm: Move SCTLR reset value setup to per cpu init fns,
Peter Maydell <=
- [Qemu-devel] [PATCH 04/14] target-arm: Move FPSID config to cpu init fns, Peter Maydell, 2012/04/21
- [Qemu-devel] [PATCH 13/14] target-arm: Drop cpu_reset_model_id(), Peter Maydell, 2012/04/21
- Re: [Qemu-devel] [PULL 00/14] target-arm queue, Blue Swirl, 2012/04/22