Re: [Qemu-devel] synching GPE0_BLK between OVMF and qemu

[Jordan Justen]

On Fri, Apr 27, 2012 at 11:47, Laszlo Ersek <address@hidden> wrote:
> This was how I interpreted our discussion with Jordan:
>
> L: Shouldn't qemu & OVMF agree on GPE0?
> J: Why? Anyway, OVMF should be correct, because all ACPI registers are
> in one tight bunch, starting from 0x400.
> L: None of those two characteristics (1: "0x400", 2: "one tight bunch")
> are required by the spec. For proof, see what SeaBIOS does: 1: it
> doesn't use 0x400 as base, 2: GPE0 is not even above the base.

This code was written to the PIIX4 datasheet. According to the
datasheet, if you change PMBA, it changes the GPE blk too.

It sounds like QEMU does not emulate this, and hardcodes the GPE blk.

Regarding a solution, such as communicating the address in fw_cfg,
that could work. OVMF has plans to add fw_cfg support.

> Anyway, back to my original question: currently OVMF and qemu disagree
> wrt. GPE0. Which one should I try to modify so that they agree?

It does seem like qemu could be changed, does it? It would require a
simultaneous fix of qemu & seabios. But, if qemu could be changed,
could it be made to match the PIIX4 datasheet?

-Jordan