[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 6/9] hw/arm_gic: Make CPU target registers RAZ/WI on
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 6/9] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor |
Date: |
Wed, 2 May 2012 18:12:09 +0100 |
The GIC spec says that the CPU target registers should RAZ/WI
for uniprocessor implementations. Implement this, which also
conveniently lets us drop an NVIC ifdef.
Annoyingly, the 11MPCore's GIC is the odd one out, since
it always has these registers, even in uniprocessor configs.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm_gic.c | 56 +++++++++++++++++++++++++++++++++-----------------------
1 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index ad72ac6..a6e2431 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -86,11 +86,7 @@ typedef struct gic_irq_state
#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
s->priority1[irq][cpu] : \
s->priority2[(irq) - GIC_INTERNAL])
-#ifdef NVIC
-#define GIC_TARGET(irq) 1
-#else
#define GIC_TARGET(irq) s->irq_target[irq]
-#endif
typedef struct gic_state
{
@@ -377,18 +373,22 @@ static uint32_t gic_dist_readb(void *opaque,
target_phys_addr_t offset)
if (irq >= s->num_irq)
goto bad_reg;
res = GIC_GET_PRIORITY(irq, cpu);
-#ifndef NVIC
} else if (offset < 0xc00) {
/* Interrupt CPU Target. */
- irq = (offset - 0x800) + GIC_BASE_IRQ;
- if (irq >= s->num_irq)
- goto bad_reg;
- if (irq >= 29 && irq <= 31) {
- res = cm;
+ if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
+ /* For uniprocessor GICs these RAZ/WI */
+ res = 0;
} else {
- res = GIC_TARGET(irq);
+ irq = (offset - 0x800) + GIC_BASE_IRQ;
+ if (irq >= s->num_irq) {
+ goto bad_reg;
+ }
+ if (irq >= 29 && irq <= 31) {
+ res = cm;
+ } else {
+ res = GIC_TARGET(irq);
+ }
}
-#endif
} else if (offset < 0xf00) {
/* Interrupt Configuration. */
irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
@@ -533,18 +533,22 @@ static void gic_dist_writeb(void *opaque,
target_phys_addr_t offset,
} else {
s->priority2[irq - GIC_INTERNAL] = value;
}
-#ifndef NVIC
} else if (offset < 0xc00) {
- /* Interrupt CPU Target. */
- irq = (offset - 0x800) + GIC_BASE_IRQ;
- if (irq >= s->num_irq)
- goto bad_reg;
- if (irq < 29)
- value = 0;
- else if (irq < GIC_INTERNAL)
- value = ALL_CPU_MASK;
- s->irq_target[irq] = value & ALL_CPU_MASK;
-#endif
+ /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
+ * annoying exception of the 11MPCore's GIC.
+ */
+ if (s->num_cpu != 1 || s->revision == REV_11MPCORE) {
+ irq = (offset - 0x800) + GIC_BASE_IRQ;
+ if (irq >= s->num_irq) {
+ goto bad_reg;
+ }
+ if (irq < 29) {
+ value = 0;
+ } else if (irq < GIC_INTERNAL) {
+ value = ALL_CPU_MASK;
+ }
+ s->irq_target[irq] = value & ALL_CPU_MASK;
+ }
} else if (offset < 0xf00) {
/* Interrupt Configuration. */
irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
@@ -733,6 +737,12 @@ static void gic_reset(DeviceState *dev)
GIC_SET_ENABLED(i, ALL_CPU_MASK);
GIC_SET_TRIGGER(i);
}
+ if (s->num_cpu == 1) {
+ /* For uniprocessor GICs all interrupts always target the sole CPU */
+ for (i = 0; i < GIC_MAXIRQ; i++) {
+ s->irq_target[i] = 1;
+ }
+ }
s->enabled = 0;
}
--
1.7.1
- [Qemu-devel] [PATCH 0/9] disentangle NVIC from ARM GIC, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 2/9] hw/arm_gic: Remove the special casing of NCPU for the NVIC, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 1/9] hw/arm_gic: Remove NVIC ifdefs from gic_state struct, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 6/9] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor,
Peter Maydell <=
- [Qemu-devel] [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 3/9] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 8/9] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 9/9] hw/armv7m_nvic: Make the NVIC a freestanding class, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 4/9] hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 5/9] hw/arm_gic: Add qdev property for GIC revision, Peter Maydell, 2012/05/02
- Re: [Qemu-devel] [PATCH 0/9] disentangle NVIC from ARM GIC, Peter Maydell, 2012/05/18