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[Qemu-devel] [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a r
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting |
Date: |
Wed, 2 May 2012 18:12:10 +0100 |
Make the minor tweaks to interrupt numbering used by the NVIC
a runtime setting rather than a compile time one, so we can
drop more NVIC ifdefs.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm_gic.c | 12 ++++--------
1 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index a6e2431..c288bc5 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -36,13 +36,9 @@ do { printf("arm_gic: " fmt , ## __VA_ARGS__); } while (0)
#define DPRINTF(fmt, ...) do {} while(0)
#endif
-#ifdef NVIC
/* The NVIC has 16 internal vectors. However these are not exposed
through the normal GIC interface. */
-#define GIC_BASE_IRQ 32
-#else
-#define GIC_BASE_IRQ 0
-#endif
+#define GIC_BASE_IRQ ((s->revision == REV_NVIC) ? 32 : 0)
static const uint8_t gic_id[] = {
0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1
@@ -839,7 +835,6 @@ static void gic_init(gic_state *s, int num_irq)
}
i = s->num_irq - GIC_INTERNAL;
-#ifndef NVIC
/* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
* GPIO array layout is thus:
* [0..N-1] SPIs
@@ -847,8 +842,9 @@ static void gic_init(gic_state *s, int num_irq)
* [N+32..N+63] PPIs for CPU 1
* ...
*/
- i += (GIC_INTERNAL * s->num_cpu);
-#endif
+ if (s->revision != REV_NVIC) {
+ i += (GIC_INTERNAL * s->num_cpu);
+ }
qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, i);
for (i = 0; i < NUM_CPU(s); i++) {
sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
--
1.7.1
- [Qemu-devel] [PATCH 0/9] disentangle NVIC from ARM GIC, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 2/9] hw/arm_gic: Remove the special casing of NCPU for the NVIC, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 1/9] hw/arm_gic: Remove NVIC ifdefs from gic_state struct, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 6/9] hw/arm_gic: Make CPU target registers RAZ/WI on uniprocessor, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 7/9] hw/arm_gic.c: Make NVIC interrupt numbering a runtime setting,
Peter Maydell <=
- [Qemu-devel] [PATCH 3/9] hw/arm_gic: Move NVIC specific reset to armv7m_nvic_reset, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 8/9] hw/arm_gic: Move CPU interface memory region setup into arm_gic_init, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 9/9] hw/armv7m_nvic: Make the NVIC a freestanding class, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 4/9] hw/armv7m_nvic: Use MemoryRegions for NVIC specific registers, Peter Maydell, 2012/05/02
- [Qemu-devel] [PATCH 5/9] hw/arm_gic: Add qdev property for GIC revision, Peter Maydell, 2012/05/02
- Re: [Qemu-devel] [PATCH 0/9] disentangle NVIC from ARM GIC, Peter Maydell, 2012/05/18