[Qemu-devel] [PATCH 13/13] iommu: Add a memory barrier to DMA RW function

[Benjamin Herrenschmidt]

From: David Gibson <address@hidden>

The emulated devices can run simultaneously with the guest, so
we need to be careful with ordering of load and stores done by
them to the guest system memory, which need to be observed in
the right order by the guest operating system.

The simplest way for now to address that is to stick a memory
barrier in the main DMA read/write function of the iommu layer,
this will make everything using that layer hopefully "just work".

We don't emulate devices supporting the relaxed ordering PCIe
feature nor do we want to look at doing more fine grained
barriers for now as it could quickly become too complex and not
worth the cost.

Note that this will not help devices using the map/unmap APIs,
those will need to use explicit barriers, similar to what
virtio does.

Signed-off-by: David Gibson <address@hidden>
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
 dma-helpers.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/dma-helpers.c b/dma-helpers.c
index 36fa963..4350cdf 100644
--- a/dma-helpers.c
+++ b/dma-helpers.c
@@ -312,6 +312,9 @@ int iommu_dma_memory_rw(DMAContext *dma, dma_addr_t addr,
         buf += plen;
     }
 
+    /* HACK: full memory barrier here */
+    __sync_synchronize();
+
     return 0;
 }
 
-- 
1.7.9.5