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[Qemu-devel] [PATCH qom-next v2 05/33] hw/pxa2xx_pic: Convert coprocesso
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH qom-next v2 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme |
Date: |
Mon, 14 May 2012 20:03:04 +0100 |
Convert the coprocessor access functions for the pxa2xx PIC to the
arm_cp_reginfo scheme.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/pxa2xx_pic.c | 53 +++++++++++++++++++++++++++++++----------------------
1 files changed, 31 insertions(+), 22 deletions(-)
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index a806b80..6ba932a 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -206,33 +206,42 @@ static const int pxa2xx_cp_reg_map[0x10] = {
[0xa] = ICPR2,
};
-static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)
+static int pxa2xx_pic_cp_read(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t *value)
{
- target_phys_addr_t offset;
-
- if (pxa2xx_cp_reg_map[reg] == -1) {
- printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
- return 0;
- }
-
- offset = pxa2xx_cp_reg_map[reg];
- return pxa2xx_pic_mem_read(opaque, offset, 4);
+ int offset = pxa2xx_cp_reg_map[ri->crn];
+ *value = pxa2xx_pic_mem_read(ri->opaque, offset, 4);
+ return 0;
}
-static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
- uint32_t value)
+static int pxa2xx_pic_cp_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
{
- target_phys_addr_t offset;
-
- if (pxa2xx_cp_reg_map[reg] == -1) {
- printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
- return;
- }
-
- offset = pxa2xx_cp_reg_map[reg];
- pxa2xx_pic_mem_write(opaque, offset, value, 4);
+ int offset = pxa2xx_cp_reg_map[ri->crn];
+ pxa2xx_pic_mem_write(ri->opaque, offset, value, 4);
+ return 0;
}
+#define REGINFO_FOR_PIC_CP(NAME, CRN) \
+ { .name = NAME, .cp = 6, .crn = CRN, .crm = 0, .opc1 = 0, .opc2 = 0, \
+ .access = PL1_RW, \
+ .readfn = pxa2xx_pic_cp_read, .writefn = pxa2xx_pic_cp_write }
+
+static const ARMCPRegInfo pxa_pic_cp_reginfo[] = {
+ REGINFO_FOR_PIC_CP("ICIP", 0),
+ REGINFO_FOR_PIC_CP("ICMR", 1),
+ REGINFO_FOR_PIC_CP("ICLR", 2),
+ REGINFO_FOR_PIC_CP("ICFP", 3),
+ REGINFO_FOR_PIC_CP("ICPR", 4),
+ REGINFO_FOR_PIC_CP("ICHP", 5),
+ REGINFO_FOR_PIC_CP("ICIP2", 6),
+ REGINFO_FOR_PIC_CP("ICMR2", 7),
+ REGINFO_FOR_PIC_CP("ICLR2", 8),
+ REGINFO_FOR_PIC_CP("ICFP2", 9),
+ REGINFO_FOR_PIC_CP("ICPR2", 0xa),
+ REGINFO_SENTINEL
+};
+
static const MemoryRegionOps pxa2xx_pic_ops = {
.read = pxa2xx_pic_mem_read,
.write = pxa2xx_pic_mem_write,
@@ -270,7 +279,7 @@ DeviceState *pxa2xx_pic_init(target_phys_addr_t base,
CPUARMState *env)
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
/* Enable IC coprocessor access. */
- cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
+ define_arm_cp_regs_with_opaque(arm_env_get_cpu(env), pxa_pic_cp_reginfo,
s);
return dev;
}
--
1.7.1
- [Qemu-devel] [PATCH qom-next v2 24/33] target-arm: Convert cp15 crn=9 registers, (continued)
- [Qemu-devel] [PATCH qom-next v2 24/33] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 20/33] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 22/33] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 08/33] target-arm: Convert debug registers to cp_reginfo, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 12/33] target-arm: Convert performance monitor registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 14/33] target-arm: Convert cp15 c3 register, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 15/33] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 13/33] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 18/33] target-arm: Convert cp15 crn=10 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 06/33] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme,
Peter Maydell <=
- [Qemu-devel] [PATCH qom-next v2 01/33] target-arm: Fix 11MPCore cache type register value, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 03/33] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 02/33] target-arm: initial coprocessor register framework, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 10/33] target-arm: Convert WFI/barriers special cases to cp_reginfo, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 07/33] target-arm: Add register_cp_regs_for_features(), Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 16/33] target-arm: Convert cp15 crn=2 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 19/33] target-arm: Convert cp15 crn=15 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 11/33] target-arm: Convert TLS registers, Peter Maydell, 2012/05/14