Re: [Qemu-devel] [PATCH 05/15] Openrisc: add exception support

[Blue Swirl]

On Thu, May 17, 2012 at 8:35 AM, Jia Liu <address@hidden> wrote:
> add the openrisc exception support.
>
> Signed-off-by: Jia Liu <address@hidden>
> ---
>  Makefile.target               |    2 +-
>  target-openrisc/excp.c        |   27 +++++++++++++++++++++++++++
>  target-openrisc/excp.h        |   28 ++++++++++++++++++++++++++++
>  target-openrisc/excp_helper.c |   28 ++++++++++++++++++++++++++++
>  target-openrisc/helper.h      |    3 +++
>  target-openrisc/translate.c   |   25 ++++++++++++++++---------
>  6 files changed, 103 insertions(+), 10 deletions(-)
>  create mode 100644 target-openrisc/excp.c
>  create mode 100644 target-openrisc/excp.h
>  create mode 100644 target-openrisc/excp_helper.c
>
> diff --git a/Makefile.target b/Makefile.target
> index 975c9a8..ed5f0b0 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -101,7 +101,7 @@ endif
>  libobj-$(TARGET_SPARC) += int32_helper.o
>  libobj-$(TARGET_SPARC64) += int64_helper.o
>  libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o
> -libobj-$(TARGET_OPENRISC) += intrp_helper.o mem.o mem_helper.o
> +libobj-$(TARGET_OPENRISC) += excp.o excp_helper.o intrp_helper.o mem.o 
> mem_helper.o
>
>  libobj-y += disas.o
>  libobj-$(CONFIG_TCI_DIS) += tci-dis.o
> diff --git a/target-openrisc/excp.c b/target-openrisc/excp.c
> new file mode 100644
> index 0000000..fc9391a
> --- /dev/null
> +++ b/target-openrisc/excp.c
> @@ -0,0 +1,27 @@
> +/*
> + *  Openrisc exception.
> + *
> + *  Copyright (c) 2011-2012 Jia Liu <address@hidden>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see 
> <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "cpu.h"
> +#include "excp.h"
> +
> +void raise_exception(CPUOPENRISCState *env, uint32_t excp)

QEMU_NORETURN?

> +{
> +    env->exception_index = excp;
> +    cpu_loop_exit(env);
> +}

I'd just merge this file with excp_helper.c for simplicity, though
it's not incorrect either.

> diff --git a/target-openrisc/excp.h b/target-openrisc/excp.h
> new file mode 100644
> index 0000000..4c32e46
> --- /dev/null
> +++ b/target-openrisc/excp.h
> @@ -0,0 +1,28 @@
> +/*
> + *  Openrisc exception header.
> + *
> + *  Copyright (c) 2011-2012 Jia Liu <address@hidden>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see 
> <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef QEMU_OPENRISC_EXCP_H
> +#define QEMU_OPENRISC_EXCP_H
> +
> +#include "cpu.h"
> +#include "qemu-common.h"
> +
> +void raise_exception(CPUOPENRISCState *env, uint32_t excp);
> +
> +#endif /* QEMU_OPENRISC_EXCP_H */
> diff --git a/target-openrisc/excp_helper.c b/target-openrisc/excp_helper.c
> new file mode 100644
> index 0000000..0cad14b
> --- /dev/null
> +++ b/target-openrisc/excp_helper.c
> @@ -0,0 +1,28 @@
> +/*
> + * OpenRISC exception helper routines
> + *
> + *  Copyright (c) 2011-2012 Jia Liu <address@hidden>
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Library General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Library General Public License for more details.
> + *
> + * You should have received a copy of the GNU Library General Public
> + * License along with this library; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 
> USA

Please use the web version instead.

> + */
> +
> +#include "cpu.h"
> +#include "helper.h"
> +#include "excp.h"
> +
> +void HELPER(exception)(CPUOPENRISCState *env, uint32_t excp)
> +{
> +    raise_exception(env, excp);
> +}
> diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
> index bb394ad..a0fb8c4 100644
> --- a/target-openrisc/helper.h
> +++ b/target-openrisc/helper.h
> @@ -20,6 +20,9 @@
>
>  #include "def-helper.h"
>
> +/* exception */
> +DEF_HELPER_FLAGS_2(exception, 0, void, env, i32)
> +
>  /* interrupt */
>  DEF_HELPER_FLAGS_1(rfe, 0, void, env)
>
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index dd0240c..a1264c9 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -155,6 +155,13 @@ static inline void gen_load_gpr(TCGv t, unsigned int reg)
>     }
>  }
>
> +static void gen_exception(DisasContext *dc, unsigned int excp)
> +{
> +    TCGv_i32 tmp = tcg_const_i32(excp);
> +    gen_helper_exception(cpu_env, tmp);
> +    tcg_temp_free(tmp);
> +}
> +
>  static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
>  {
>     TranslationBlock *tb;
> @@ -167,7 +174,7 @@ static void gen_goto_tb(DisasContext *dc, int n, 
> target_ulong dest)
>     } else {
>         tcg_gen_movi_tl(cpu_pc, dest);
>         if (dc->singlestep_enabled) {
> -            /* exception here */
> +            gen_exception(dc, EXCP_DEBUG);
>         }
>         tcg_gen_exit_tb(0);
>     }
> @@ -281,7 +288,7 @@ static void dec_calc(DisasContext *dc, CPUOPENRISCState 
> *env, uint32_t insn)
>             if (rb != 0) {
>                 tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
>             } else {
> -                /* exception here */
> +                gen_exception(dc, EXCP_RANGE);
>             }
>             break;
>         default:
> @@ -296,7 +303,7 @@ static void dec_calc(DisasContext *dc, CPUOPENRISCState 
> *env, uint32_t insn)
>             if (rb != 0) {
>                 tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
>             } else {
> -                /* exception here */
> +                gen_exception(dc, EXCP_RANGE);
>             }
>             break;
>         default:
> @@ -1003,14 +1010,14 @@ static void dec_sys(DisasContext *dc, 
> CPUOPENRISCState *env, uint32_t insn)
>     case 0x000:  /*l.sys*/
>         /*LOG_DIS("l.sys %d\n", K16);*/
>         tcg_gen_movi_tl(cpu_pc, dc->pc);
> -        /* exception here */
> +        gen_exception(dc, EXCP_SYSCALL);
>         dc->is_jmp = DISAS_UPDATE;
>         break;
>
>     case 0x100:  /*l.trap*/
>         /*LOG_DIS("l.trap %d\n", K16);*/
>         tcg_gen_movi_tl(cpu_pc, dc->pc);
> -        /* exception here */
> +        gen_exception(dc, EXCP_TRAP);
>         break;
>
>     case 0x300:  /*l.csync*/
> @@ -1085,7 +1092,7 @@ static void dec_float(DisasContext *dc, 
> CPUOPENRISCState *env, uint32_t insn)
>         if (cpu_R[rb] != 0) {
>             tcg_gen_div_i64(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
>         } else {
> -            /* exception here */
> +            gen_exception(dc, EXCP_RANGE);
>         }
>         break;
>
> @@ -1094,7 +1101,7 @@ static void dec_float(DisasContext *dc, 
> CPUOPENRISCState *env, uint32_t insn)
>         if (cpu_R[rb] != 0) {
>             tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
>         } else {
> -            /* exception here */
> +            gen_exception(dc, EXCP_RANGE);
>         }
>         break;
>
> @@ -1294,7 +1301,7 @@ static void check_breakpoint(CPUOPENRISCState *env, 
> DisasContext *dc)
>         QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
>             if (bp->pc == dc->pc) {
>                 tcg_gen_movi_tl(cpu_pc, dc->pc);
> -                /* exception here */
> +                gen_exception(dc, EXCP_DEBUG);
>                 dc->is_jmp = DISAS_UPDATE;
>             }
>         }
> @@ -1403,7 +1410,7 @@ static inline void 
> gen_intermediate_code_internal(CPUOPENRISCState *env,
>         if (dc->is_jmp == DISAS_NEXT) {
>             tcg_gen_movi_tl(cpu_pc, dc->pc);
>         }
> -        /* exception here*/
> +        gen_exception(dc, EXCP_DEBUG);
>     } else {
>         switch (dc->is_jmp) {
>         case DISAS_NEXT:
> --
> 1.7.9.5
>
>