Re: [Qemu-devel] [PATCH 13/13] iommu: Add a memory barrier to DMA RW function

[Benjamin Herrenschmidt]

On Sat, 2012-05-19 at 09:24 +0200, Paolo Bonzini wrote:

> I guess the C11/C++ guys required an isync barrier after either loads or
> stores, because they need to order the load/store vs. code accessing
> other memory.  This is not needed in QEMU because all guest accesses go
> through cpu_physical_memory_rw (or has its own barriers).

I am not sure, I don't quite see what it buys them really. I'd have to
ask Paul McKenney, he probably knows :-)

Cheers,
Ben.