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[Qemu-devel] [PATCH 1.1 3/6] target-xtensa: extract TLB entry setting me
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 1.1 3/6] target-xtensa: extract TLB entry setting method |
Date: |
Sun, 27 May 2012 18:34:51 +0400 |
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/cpu.h | 3 +++
target-xtensa/op_helper.c | 15 +++++++++++----
2 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 6d0ea7c..6c590fe 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -370,6 +370,9 @@ void split_tlb_entry_spec_way(const CPUXtensaState *env,
uint32_t v, bool dtlb,
uint32_t *vpn, uint32_t wi, uint32_t *ei);
int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
uint32_t *pwi, uint32_t *pei, uint8_t *pring);
+void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
+ xtensa_tlb_entry *entry, bool dtlb,
+ unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
int xtensa_get_physical_addr(CPUXtensaState *env,
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index ce61157..663bb6d 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -655,6 +655,16 @@ uint32_t HELPER(ptlb)(uint32_t v, uint32_t dtlb)
}
}
+void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
+ xtensa_tlb_entry *entry, bool dtlb,
+ unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
+{
+ entry->vaddr = vpn;
+ entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
+ entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
+ entry->attr = pte & 0xf;
+}
+
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{
@@ -665,10 +675,7 @@ void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
if (entry->asid) {
tlb_flush_page(env, entry->vaddr);
}
- entry->vaddr = vpn;
- entry->paddr = pte & xtensa_tlb_get_addr_mask(env, dtlb, wi);
- entry->asid = (env->sregs[RASID] >> ((pte >> 1) & 0x18)) & 0xff;
- entry->attr = pte & 0xf;
+ xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
tlb_flush_page(env, entry->vaddr);
} else {
qemu_log("%s %d, %d, %d trying to set immutable entry\n",
--
1.7.7.6
- [Qemu-devel] [PULL 1.1 0/6] target-xtensa MMU fixes, Max Filippov, 2012/05/27
- [Qemu-devel] [PATCH 1.1 1/6] target-xtensa: flush TLB page for new MMU mapping, Max Filippov, 2012/05/27
- [Qemu-devel] [PATCH 1.1 2/6] target-xtensa: update EXCVADDR in case of page table lookup, Max Filippov, 2012/05/27
- [Qemu-devel] [PATCH 1.1 3/6] target-xtensa: extract TLB entry setting method,
Max Filippov <=
- [Qemu-devel] [PATCH 1.1 4/6] target-xtensa: update autorefill TLB entries conditionally, Max Filippov, 2012/05/27
- [Qemu-devel] [PATCH 1.1 5/6] target-xtensa: control page table lookup explicitly, Max Filippov, 2012/05/27
- [Qemu-devel] [PATCH 1.1 6/6] target-xtensa: add MMU pagewalking tests, Max Filippov, 2012/05/27
- Re: [Qemu-devel] [PULL 1.1 0/6] target-xtensa MMU fixes, Andreas Färber, 2012/05/27