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[Qemu-devel] [PATCH 04/13] pci: Rename map_irq to route_pin
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From: |
Jan Kiszka |
|
Subject: |
[Qemu-devel] [PATCH 04/13] pci: Rename map_irq to route_pin |
|
Date: |
Mon, 4 Jun 2012 10:52:12 +0200 |
To avoid confusion with the board-level IRQ the host bridge triggers on
output, rename the per-bridge routing function for the INTx pins to
pci_route_pin_fn. Also adjust variable names of that type. And
rename pci_bridge_map_irq to pci_bridge_prepare, which better reflects
the job of that function.
Signed-off-by: Jan Kiszka <address@hidden>
---
hw/alpha_sys.h | 2 +-
hw/alpha_typhoon.c | 2 +-
hw/apb_pci.c | 4 ++--
hw/dec_pci.c | 2 +-
hw/ioh3420.c | 5 +++--
hw/ioh3420.h | 3 ++-
hw/pci.c | 14 ++++++++------
hw/pci.h | 8 +++++---
hw/pci_bridge.c | 10 +++++-----
hw/pci_bridge.h | 4 ++--
hw/pci_bridge_dev.c | 7 ++++---
hw/pci_internals.h | 4 ++--
hw/xio3130_downstream.c | 5 +++--
hw/xio3130_downstream.h | 3 ++-
hw/xio3130_upstream.c | 5 +++--
hw/xio3130_upstream.h | 3 ++-
16 files changed, 46 insertions(+), 35 deletions(-)
diff --git a/hw/alpha_sys.h b/hw/alpha_sys.h
index de40f8b..ddeb360 100644
--- a/hw/alpha_sys.h
+++ b/hw/alpha_sys.h
@@ -12,7 +12,7 @@
PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, CPUAlphaState *[4],
- pci_map_irq_fn);
+ pci_route_pin_fn);
/* alpha_pci.c. */
extern const MemoryRegionOps alpha_pci_bw_io_ops;
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c
index 872e112..d5193bb 100644
--- a/hw/alpha_typhoon.c
+++ b/hw/alpha_typhoon.c
@@ -693,7 +693,7 @@ static void typhoon_alarm_timer(void *opaque)
PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus,
qemu_irq *p_rtc_irq,
- CPUAlphaState *cpus[4], pci_map_irq_fn sys_map_irq)
+ CPUAlphaState *cpus[4], pci_route_pin_fn sys_map_irq)
{
const uint64_t MB = 1024 * 1024;
const uint64_t GB = 1024 * MB;
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index c28411a..57ead09 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -392,7 +392,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true,
"pbm-bridge");
br = DO_UPCAST(PCIBridge, dev, pci_dev);
- pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1",
+ pci_bridge_prepare(br, "Advanced PCI Bus secondary bridge 1",
pci_apb_map_irq);
qdev_init_nofail(&pci_dev->qdev);
*bus2 = pci_bridge_get_sec_bus(br);
@@ -400,7 +400,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
pci_dev = pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true,
"pbm-bridge");
br = DO_UPCAST(PCIBridge, dev, pci_dev);
- pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2",
+ pci_bridge_prepare(br, "Advanced PCI Bus secondary bridge 2",
pci_apb_map_irq);
qdev_init_nofail(&pci_dev->qdev);
*bus3 = pci_bridge_get_sec_bus(br);
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index 37337bf..be63ac7 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -81,7 +81,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
dev = pci_create_multifunction(parent_bus, devfn, false,
"dec-21154-p2p-bridge");
br = DO_UPCAST(PCIBridge, dev, dev);
- pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
+ pci_bridge_prepare(br, "DEC 21154 PCI-PCI bridge", dec_map_irq);
qdev_init_nofail(&dev->qdev);
return pci_bridge_get_sec_bus(br);
}
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 1632d31..21bc1fb 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -164,7 +164,8 @@ static int ioh3420_exitfn(PCIDevice *d)
}
PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
- const char *bus_name, pci_map_irq_fn map_irq,
+ const char *bus_name,
+ pci_route_pin_fn route_intx_pin,
uint8_t port, uint8_t chassis, uint16_t slot)
{
PCIDevice *d;
@@ -178,7 +179,7 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool
multifunction,
br = DO_UPCAST(PCIBridge, dev, d);
qdev = &br->dev.qdev;
- pci_bridge_map_irq(br, bus_name, map_irq);
+ pci_bridge_prepare(br, bus_name, route_intx_pin);
qdev_prop_set_uint8(qdev, "port", port);
qdev_prop_set_uint8(qdev, "chassis", chassis);
qdev_prop_set_uint16(qdev, "slot", slot);
diff --git a/hw/ioh3420.h b/hw/ioh3420.h
index 68c523a..091bef4 100644
--- a/hw/ioh3420.h
+++ b/hw/ioh3420.h
@@ -4,7 +4,8 @@
#include "pcie_port.h"
PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
- const char *bus_name, pci_map_irq_fn map_irq,
+ const char *bus_name,
+ pci_route_pin_fn route_intx_pin,
uint8_t port, uint8_t chassis, uint16_t slot);
#endif /* QEMU_IOH3420_H */
diff --git a/hw/pci.c b/hw/pci.c
index 771fb39..9a2b4a3 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -121,7 +121,7 @@ static void pci_set_device_intx_routing(PCIBus *bus,
PCIDevice *dev)
/* We might be too early, i.e. before pci_bus_irqs was called.
* We will be called again when this happened. */
- if (!bus->map_irq) {
+ if (!bus->route_intx_pin) {
return;
}
@@ -130,7 +130,7 @@ static void pci_set_device_intx_routing(PCIBus *bus,
PCIDevice *dev)
output_pin = pin;
do {
bus = pci_dev->bus;
- output_pin = bus->map_irq(pci_dev, output_pin);
+ output_pin = bus->route_intx_pin(pci_dev, output_pin);
pci_dev = bus->parent_dev;
} while (pci_dev);
@@ -318,11 +318,12 @@ PCIBus *pci_bus_new(DeviceState *parent, const char *name,
return bus;
}
-void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
+ pci_route_pin_fn route_intx_pin,
void *irq_opaque, int nirq)
{
bus->set_irq = set_irq;
- bus->map_irq = map_irq;
+ bus->route_intx_pin = route_intx_pin;
bus->irq_opaque = irq_opaque;
bus->nirq = nirq;
bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
@@ -337,7 +338,8 @@ void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug,
DeviceState *qdev)
}
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
- pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+ pci_set_irq_fn set_irq,
+ pci_route_pin_fn route_intx_pin,
void *irq_opaque,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
@@ -347,7 +349,7 @@ PCIBus *pci_register_bus(DeviceState *parent, const char
*name,
bus = pci_bus_new(parent, name, address_space_mem,
address_space_io, devfn_min);
- pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
+ pci_bus_irqs(bus, set_irq, route_intx_pin, irq_opaque, nirq);
return bus;
}
diff --git a/hw/pci.h b/hw/pci.h
index c4fd863..5b54e2d 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -279,7 +279,7 @@ MemoryRegion *pci_address_space(PCIDevice *dev);
MemoryRegion *pci_address_space_io(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
-typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
+typedef int (*pci_route_pin_fn)(PCIDevice *pci_dev, int pin);
typedef enum {
PCI_HOTPLUG_DISABLED,
@@ -293,12 +293,14 @@ PCIBus *pci_bus_new(DeviceState *parent, const char *name,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
uint8_t devfn_min);
-void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
+ pci_route_pin_fn route_intx_pin,
void *irq_opaque, int nirq);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
- pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
+ pci_set_irq_fn set_irq,
+ pci_route_pin_fn route_intx_pin,
void *irq_opaque,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c
index 866f0b6..7d13a85 100644
--- a/hw/pci_bridge.c
+++ b/hw/pci_bridge.c
@@ -327,7 +327,7 @@ int pci_bridge_initfn(PCIDevice *dev)
qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev,
br->bus_name);
sec_bus->parent_dev = dev;
- sec_bus->map_irq = br->map_irq;
+ sec_bus->route_intx_pin = br->route_intx_pin;
sec_bus->address_space_mem = &br->address_space_mem;
memory_region_init(&br->address_space_mem, "pci_bridge_pci", INT64_MAX);
sec_bus->address_space_io = &br->address_space_io;
@@ -353,12 +353,12 @@ int pci_bridge_exitfn(PCIDevice *pci_dev)
/*
* before qdev initialization(qdev_init()), this function sets bus_name and
- * map_irq callback which are necessry for pci_bridge_initfn() to
+ * route_intx_pin callback which are necessry for pci_bridge_initfn() to
* initialize bus.
*/
-void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
- pci_map_irq_fn map_irq)
+void pci_bridge_prepare(PCIBridge *br, const char* bus_name,
+ pci_route_pin_fn route_intx_pin)
{
- br->map_irq = map_irq;
+ br->route_intx_pin = route_intx_pin;
br->bus_name = bus_name;
}
diff --git a/hw/pci_bridge.h b/hw/pci_bridge.h
index 84411a6..ac019a9 100644
--- a/hw/pci_bridge.h
+++ b/hw/pci_bridge.h
@@ -52,8 +52,8 @@ int pci_bridge_exitfn(PCIDevice *pci_dev);
* map_irq callback which are necessry for pci_bridge_initfn() to
* initialize bus.
*/
-void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
- pci_map_irq_fn map_irq);
+void pci_bridge_prepare(PCIBridge *br, const char* bus_name,
+ pci_route_pin_fn route_intx_pin);
#endif /* QEMU_PCI_BRIDGE_H */
/*
diff --git a/hw/pci_bridge_dev.c b/hw/pci_bridge_dev.c
index eccaa58..d5a14a9 100644
--- a/hw/pci_bridge_dev.c
+++ b/hw/pci_bridge_dev.c
@@ -43,9 +43,9 @@ typedef struct PCIBridgeDev PCIBridgeDev;
/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
* revision 1.2 */
/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
-static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
+static int pci_bridge_dev_route_intx_pin(PCIDevice *dev, int pin)
{
- return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
+ return (pin + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
}
static int pci_bridge_dev_initfn(PCIDevice *dev)
@@ -53,7 +53,8 @@ static int pci_bridge_dev_initfn(PCIDevice *dev)
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
int err;
- pci_bridge_map_irq(br, NULL, pci_bridge_dev_map_irq_fn);
+
+ pci_bridge_prepare(br, NULL, pci_bridge_dev_route_intx_pin);
err = pci_bridge_initfn(dev);
if (err) {
goto bridge_error;
diff --git a/hw/pci_internals.h b/hw/pci_internals.h
index 96690b7..be5594b 100644
--- a/hw/pci_internals.h
+++ b/hw/pci_internals.h
@@ -18,7 +18,7 @@ struct PCIBus {
BusState qbus;
uint8_t devfn_min;
pci_set_irq_fn set_irq;
- pci_map_irq_fn map_irq;
+ pci_route_pin_fn route_intx_pin;
pci_hotplug_fn hotplug;
DeviceState *hotplug_qdev;
void *irq_opaque;
@@ -59,7 +59,7 @@ struct PCIBridge {
MemoryRegion alias_pref_mem;
MemoryRegion alias_mem;
MemoryRegion alias_io;
- pci_map_irq_fn map_irq;
+ pci_route_pin_fn route_intx_pin;
const char *bus_name;
};
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index 319624f..d334e16 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -128,7 +128,8 @@ static int xio3130_downstream_exitfn(PCIDevice *d)
}
PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
- const char *bus_name, pci_map_irq_fn map_irq,
+ const char *bus_name,
+ pci_route_pin_fn route_intx_pin,
uint8_t port, uint8_t chassis,
uint16_t slot)
{
@@ -144,7 +145,7 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn,
bool multifunction,
br = DO_UPCAST(PCIBridge, dev, d);
qdev = &br->dev.qdev;
- pci_bridge_map_irq(br, bus_name, map_irq);
+ pci_bridge_prepare(br, bus_name, route_intx_pin);
qdev_prop_set_uint8(qdev, "port", port);
qdev_prop_set_uint8(qdev, "chassis", chassis);
qdev_prop_set_uint16(qdev, "slot", slot);
diff --git a/hw/xio3130_downstream.h b/hw/xio3130_downstream.h
index 010487f..c4941bd 100644
--- a/hw/xio3130_downstream.h
+++ b/hw/xio3130_downstream.h
@@ -4,7 +4,8 @@
#include "pcie_port.h"
PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
- const char *bus_name, pci_map_irq_fn map_irq,
+ const char *bus_name,
+ pci_route_pin_fn route_intx_pin,
uint8_t port, uint8_t chassis,
uint16_t slot);
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index 34a99bb..39a8189 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -110,7 +110,8 @@ static int xio3130_upstream_exitfn(PCIDevice *d)
}
PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
- const char *bus_name, pci_map_irq_fn map_irq,
+ const char *bus_name,
+ pci_route_pin_fn route_intx_pin,
uint8_t port)
{
PCIDevice *d;
@@ -124,7 +125,7 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn,
bool multifunction,
br = DO_UPCAST(PCIBridge, dev, d);
qdev = &br->dev.qdev;
- pci_bridge_map_irq(br, bus_name, map_irq);
+ pci_bridge_prepare(br, bus_name, route_intx_pin);
qdev_prop_set_uint8(qdev, "port", port);
qdev_init_nofail(qdev);
diff --git a/hw/xio3130_upstream.h b/hw/xio3130_upstream.h
index e996997..bf3784e 100644
--- a/hw/xio3130_upstream.h
+++ b/hw/xio3130_upstream.h
@@ -4,7 +4,8 @@
#include "pcie_port.h"
PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
- const char *bus_name, pci_map_irq_fn map_irq,
+ const char *bus_name,
+ pci_route_pin_fn route_intx_pin,
uint8_t port);
#endif /* QEMU_XIO3130_H */
--
1.7.3.4
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, (continued)
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, Jan Kiszka, 2012/06/10
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, Michael S. Tsirkin, 2012/06/10
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, Jan Kiszka, 2012/06/10
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, Michael S. Tsirkin, 2012/06/10
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, Jan Kiszka, 2012/06/10
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, Michael S. Tsirkin, 2012/06/10
- Re: [Qemu-devel] [PATCH 06/13] pci: Add INTx routing notifier, Michael S. Tsirkin, 2012/06/10
[Qemu-devel] [PATCH 09/13] pci: Introduce and apply PCIDeviceAddress, Jan Kiszka, 2012/06/04
[Qemu-devel] [PATCH 04/13] pci: Rename map_irq to route_pin,
Jan Kiszka <=
[Qemu-devel] [PATCH 07/13] pci: Make domain and bus unsigned in pci_read_devaddr, Jan Kiszka, 2012/06/04
[Qemu-devel] [PATCH 08/13] pci: Export pci_parse_devaddr instead of pci_read_devaddr, Jan Kiszka, 2012/06/04
[Qemu-devel] [PATCH 05/13] pci: Add pci_device_route_intx_to_irq, Jan Kiszka, 2012/06/04