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[Qemu-devel] [PATCH 29/31] PPC: e500: Extend address/size of / to 64bit
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 29/31] PPC: e500: Extend address/size of / to 64bit |
Date: |
Wed, 6 Jun 2012 01:53:20 +0200 |
We want to be able to support >= 4GB of RAM. To do so, we need to be able
to tell the guest OS how much RAM it has.
However, that information today is capped to 32bit. So let's extend the
offset and size fields to 64bit, so we can fit in big addresses and even
one day - if we wish to do so - map devices above 32bit.
Signed-off-by: Alexander Graf <address@hidden>
---
hw/ppce500_mpc8544ds.c | 28 ++++++++++++++++++----------
1 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 2815340..6c01093 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -90,7 +90,7 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
const char *kernel_cmdline)
{
int ret = -1;
- uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
+ uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
int fdt_size;
void *fdt;
uint8_t hypercall[16];
@@ -108,9 +108,16 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
char gutil[128];
char pci[128];
uint32_t pci_map[9 * 8];
- uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0,
- 0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000,
- 0x0, 0x10000 };
+ uint32_t pci_ranges[14] =
+ {
+ 0x2000000, 0x0, 0xc0000000,
+ 0x0, 0xc0000000,
+ 0x0, 0x20000000,
+
+ 0x1000000, 0x0, 0x0,
+ 0x0, 0xe1000000,
+ 0x0, 0x10000,
+ };
QemuOpts *machine_opts;
const char *dumpdtb = NULL;
const char *dtb_file = NULL;
@@ -144,8 +151,8 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_string(fdt, "/", "model", model);
qemu_devtree_setprop(fdt, "/", "compatible", compatible,
sizeof(compatible));
- qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1);
- qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1);
+ qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
+ qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
qemu_devtree_add_subnode(fdt, "/memory");
qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
@@ -239,7 +246,8 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
sizeof(compatible_sb));
qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
- qemu_devtree_setprop_cell3(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE,
+ qemu_devtree_setprop_cell4(fdt, soc, "ranges", 0x0,
+ MPC8544_CCSRBAR_BASE >> 32,
MPC8544_CCSRBAR_BASE,
MPC8544_CCSRBAR_SIZE);
/* XXX should contain a reasonable value */
qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
@@ -313,12 +321,12 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
qemu_devtree_setprop_cell4(fdt, pci, "interrupts", 24, 2, 0, 0);
qemu_devtree_setprop_cell2(fdt, pci, "bus-range", 0, 255);
- for (i = 0; i < 12; i++) {
+ for (i = 0; i < 14; i++) {
pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
}
qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
- qemu_devtree_setprop_cell2(fdt, pci, "reg", MPC8544_PCI_REGS_BASE,
- 0x1000);
+ qemu_devtree_setprop_cell4(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
+ MPC8544_PCI_REGS_BASE, 0, 0x1000);
qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
--
1.6.0.2
- [Qemu-devel] [PATCH 12/31] PPC: e500: dt: create /hypervisor node dynamically, (continued)
- [Qemu-devel] [PATCH 12/31] PPC: e500: dt: create /hypervisor node dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 10/31] PPC: e500: dt: create memory node dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 11/31] PPC: e500: dt: create /cpus node dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 13/31] PPC: e500: dt: create / node dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 15/31] PPC: e500: dt: create /soc8544 node dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 16/31] PPC: e500: dt: create serial nodes dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 17/31] PPC: e500: dt: create mpic node dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 19/31] PPC: e500: dt: create pci node dynamically, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 28/31] PPC: e500: Define addresses as always 64bit, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 20/31] PPC: e500: dt: start with empty device tree, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 29/31] PPC: e500: Extend address/size of / to 64bit,
Alexander Graf <=
- [Qemu-devel] [PATCH 25/31] Revert "dt: temporarily disable subtree creation failure check", Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 27/31] PPC: e500: Use new SOC dt format, Alexander Graf, 2012/06/05
- [Qemu-devel] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, Alexander Graf, 2012/06/05
- Re: [Qemu-devel] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, Peter Crosthwaite, 2012/06/06
- Re: [Qemu-devel] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, Alexander Graf, 2012/06/06
- Re: [Qemu-devel] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, Scott Wood, 2012/06/06
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, David Gibson, 2012/06/06
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, Alexander Graf, 2012/06/07
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, David Gibson, 2012/06/07
- Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/31] dt: add helpers for 2, 3 and 4 cell adds, Alexander Graf, 2012/06/08