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[Qemu-devel] [PATCH v3 06/16] target-or32: Add int instruction helpers
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH v3 06/16] target-or32: Add int instruction helpers |
Date: |
Wed, 6 Jun 2012 20:27:02 +0800 |
Add OpenRISC int instruction helpers.
Signed-off-by: Jia Liu <address@hidden>
---
Makefile.target | 4 +-
target-openrisc/helper.h | 8 +++
target-openrisc/int_helper.c | 155 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 165 insertions(+), 2 deletions(-)
create mode 100644 target-openrisc/int_helper.c
diff --git a/Makefile.target b/Makefile.target
index 0ce85cb..4f40fa5 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -103,8 +103,8 @@ endif
libobj-$(TARGET_SPARC) += int32_helper.o
libobj-$(TARGET_SPARC64) += int64_helper.o
libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o
-libobj-$(TARGET_OPENRISC) += excp.o excp_helper.o intrpt.o intrpt_helper.o \
- mmu.o mmu_helper.o
+libobj-$(TARGET_OPENRISC) += excp.o excp_helper.o int_helper.o intrpt.o \
+ intrpt_helper.o mmu.o mmu_helper.o
libobj-y += disas.o
libobj-$(CONFIG_TCI_DIS) += tci-dis.o
diff --git a/target-openrisc/helper.h b/target-openrisc/helper.h
index 4e2a49f..df354a5 100644
--- a/target-openrisc/helper.h
+++ b/target-openrisc/helper.h
@@ -22,6 +22,14 @@
/* exception */
DEF_HELPER_FLAGS_2(exception, 0, void, env, i32)
+/* int */
+DEF_HELPER_FLAGS_1(ff1, 0, tl, tl)
+DEF_HELPER_FLAGS_1(fl1, 0, tl, tl)
+DEF_HELPER_FLAGS_3(add, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(addc, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(sub, 0, tl, env, tl, tl)
+DEF_HELPER_FLAGS_3(mul, 0, tl, env, tl, tl)
+
/* interrupt */
DEF_HELPER_FLAGS_1(rfe, 0, void, env)
diff --git a/target-openrisc/int_helper.c b/target-openrisc/int_helper.c
new file mode 100644
index 0000000..ee5a98d
--- /dev/null
+++ b/target-openrisc/int_helper.c
@@ -0,0 +1,155 @@
+/*
+ * OpenRISC int helper routines
+ *
+ * Copyright (c) 2011-2012 Jia Liu <address@hidden>
+ * Feng Gao <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "cpu.h"
+#include "helper.h"
+#include "excp.h"
+
+target_ulong HELPER(ff1)(target_ulong x)
+{
+ target_ulong n = 0;
+
+ if (x == 0) {
+ return 0;
+ }
+
+ for (n = 32; x; n--) {
+ x <<= 1;
+ }
+ return n+1;
+}
+
+target_ulong HELPER(fl1)(target_ulong x)
+{
+ target_ulong n = 0;
+
+ if (x == 0) {
+ return 0;
+ }
+
+ for (n = 0; x; n++) {
+ x >>= 1;
+ }
+ return n;
+}
+
+target_ulong HELPER(add)(CPUOpenRISCState * env, target_ulong a, target_ulong
b)
+{
+ target_ulong result;
+ result = a + b;
+
+ if (result < a) {
+ env->sr |= SR_CY;
+ } else {
+ env->sr &= ~SR_CY;
+ }
+
+ if ((a ^ b ^ -1) & (a ^ result)) {
+ env->sr |= SR_OV;
+ if (env->sr & SR_OVE) {
+ raise_exception(env, EXCP_RANGE);
+ }
+ } else {
+ env->sr &= ~SR_OV;
+ }
+ return result;
+}
+
+target_ulong HELPER(addc)(CPUOpenRISCState * env,
+ target_ulong a, target_ulong b)
+{
+ target_ulong result;
+ int cf = env->sr & SR_CY;
+
+ if (!cf) {
+ result = a + b;
+ cf = result < a;
+ } else {
+ result = a + b + 1;
+ cf = result <= a;
+ }
+
+ if (cf) {
+ env->sr |= SR_CY;
+ } else {
+ env->sr &= ~SR_CY;
+ }
+
+ if ((a ^ b ^ -1) & (a ^ result)) {
+ env->sr |= SR_OV;
+ if (env->sr & SR_OVE) {
+ raise_exception(env, EXCP_RANGE);
+ }
+ } else {
+ env->sr &= ~SR_OV;
+ }
+ return result;
+}
+
+target_ulong HELPER(sub)(CPUOpenRISCState * env, target_ulong a, target_ulong
b)
+{
+ target_ulong result;
+ result = a - b;
+ if (a >= b) {
+ env->sr |= SR_CY;
+ } else {
+ env->sr &= ~SR_CY;
+ }
+
+ if ((a ^ b) & (a ^ result)) {
+ env->sr |= SR_OV;
+ if (env->sr & SR_OVE) {
+ raise_exception(env, EXCP_RANGE);
+ }
+ } else {
+ env->sr &= ~SR_OV;
+ }
+ return result;
+}
+
+target_ulong HELPER(mul)(CPUOpenRISCState * env, target_ulong a, target_ulong
b)
+{
+ uint64_t result;
+ result = a * b;
+ target_ulong high;
+
+ high = result >> (sizeof(target_ulong) * 8);
+
+ if (((result >> ((sizeof(target_ulong) * 8) - 1)) & 0x1) == 0) {
+ if (high == 0) {
+ return result;
+ }
+ }
+
+ if (((result >> ((sizeof(target_ulong) * 8) - 1)) & 0x1) == 1) {
+ if (high == 0xffffffff) {
+ return result;
+ }
+ }
+
+ env->sr |= SR_OV;
+ env->sr |= SR_CY;
+
+ if (env->sr & SR_OVE) {
+ raise_exception(env, EXCP_RANGE);
+ }
+
+ return result;
+}
--
1.7.9.5
- [Qemu-devel] [PATCH v3 00/16] target-or32: QEMU OpenRISC support, Jia Liu, 2012/06/06
- [Qemu-devel] [PATCH v3 01/16] target-or32: Add target stubs and cpu QOM, Jia Liu, 2012/06/06
- [Qemu-devel] [PATCH v3 02/16] target-or32: Add target machine, Jia Liu, 2012/06/06
- [Qemu-devel] [PATCH v3 03/16] target-or32: Add MMU support, Jia Liu, 2012/06/06
- [Qemu-devel] [PATCH v3 04/16] target-or32: Add interrupt support, Jia Liu, 2012/06/06
- [Qemu-devel] [PATCH v3 05/16] target-or32: Add exception support, Jia Liu, 2012/06/06
- [Qemu-devel] [PATCH v3 06/16] target-or32: Add int instruction helpers,
Jia Liu <=
- [Qemu-devel] [PATCH v3 07/16] target-or32: Add float instruction helpers, Jia Liu, 2012/06/06
- [Qemu-devel] [PATCH v3 08/16] target-or32: Add translation routines, Jia Liu, 2012/06/06