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[Qemu-devel] [PATCH v4 02/16] target-or32: Add target machine
From: |
Jia Liu |
Subject: |
[Qemu-devel] [PATCH v4 02/16] target-or32: Add target machine |
Date: |
Mon, 11 Jun 2012 14:31:50 +0800 |
Add OpenRISC target machine.
Signed-off-by: Jia Liu <address@hidden>
---
target-openrisc/cpu.h | 67 ++++++++++++++++++++++++++++++++++++++++++++-
target-openrisc/machine.c | 22 ++++++++++++++-
2 files changed, 87 insertions(+), 2 deletions(-)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 9f9f4b5..498075a 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -44,6 +44,15 @@ struct CPUOpenRISCState;
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#define SET_FP_CAUSE(reg, v) do {\
+ (reg) = ((reg) & ~(0x3f << 12)) | \
+ ((v & 0x3f) << 12);\
+ } while (0)
+#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
+#define UPDATE_FP_FLAGS(reg, v) do {\
+ (reg) |= ((v & 0x1f) << 2);\
+ } while (0)
+
/* Internel flags, delay slot flag */
#define D_FLAG 1
@@ -117,6 +126,40 @@ enum {
IMMUCFGR_HTR = (1 << 11),
};
+/* Float piont control status register */
+enum {
+ FPCSR_FPEE = 1,
+ FPCSR_RM = (3 << 1),
+ FPCSR_OVF = (1 << 3),
+ FPCSR_UNF = (1 << 4),
+ FPCSR_SNF = (1 << 5),
+ FPCSR_QNF = (1 << 6),
+ FPCSR_ZF = (1 << 7),
+ FPCSR_IXF = (1 << 8),
+ FPCSR_IVF = (1 << 9),
+ FPCSR_INF = (1 << 10),
+ FPCSR_DZF = (1 << 11),
+};
+
+/* Exceptions indices */
+enum {
+ EXCP_RESET = 0x1,
+ EXCP_BUSERR = 0x2,
+ EXCP_DPF = 0x3,
+ EXCP_IPF = 0x4,
+ EXCP_TICK = 0x5,
+ EXCP_ALIGN = 0x6,
+ EXCP_ILLEGAL = 0x7,
+ EXCP_INT = 0x8,
+ EXCP_DTLBMISS = 0x9,
+ EXCP_ITLBMISS = 0xa,
+ EXCP_RANGE = 0xb,
+ EXCP_SYSCALL = 0xc,
+ EXCP_FPE = 0xd,
+ EXCP_TRAP = 0xe,
+ EXCP_NR,
+};
+
/* Supervisor register */
enum {
SR_SM = 1,
@@ -151,6 +194,14 @@ enum {
OPENRISC_FEATURE_OR1200,
};
+/* Tick Timer Mode Register */
+enum {
+ TTMR_TP = (0xfffffff),
+ TTMR_IP = (1 << 28),
+ TTMR_IE = (1 << 29),
+ TTMR_M = (3 << 30),
+};
+
typedef struct CPUOpenRISCState CPUOpenRISCState;
struct CPUOpenRISCState {
target_ulong gpr[32]; /* General registers */
@@ -159,12 +210,25 @@ struct CPUOpenRISCState {
target_ulong ppc; /* Prev PC */
target_ulong jmp_pc; /* Jump PC */
+ target_ulong machi; /* Multiply register MACHI */
+ target_ulong maclo; /* Multiply register MACLO */
+
+ target_ulong fpmaddhi; /* Multiply and add float register FPMADDHI */
+ target_ulong fpmaddlo; /* Multiply and add float register FPMADDLO */
+
+ target_ulong epcr; /* Exception PC register */
+ target_ulong eear; /* Exception EA register */
+
uint32_t sr; /* Supervisor register */
uint32_t vr; /* Version register */
uint32_t upr; /* Unit presence register */
uint32_t cpucfgr; /* CPU configure register */
uint32_t dmmucfgr; /* DMMU configure register */
uint32_t immucfgr; /* IMMU configure register */
+ uint32_t esr; /* Exception supervisor register */
+ uint32_t fpcsr; /* Float register */
+ float_status fp_status;
+
uint32_t flags; /* cpu_flags, we only use it for exception
in solt so far. */
uint32_t btaken; /* the SR_F bit */
@@ -265,7 +329,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState
*env,
{
*pc = env->pc;
*cs_base = 0;
- *flags = 0;
+ /* D_FLAG -- branch insrtuction exception */
+ *flags = (env->flags&D_FLAG);
}
static inline int cpu_mmu_index(CPUOpenRISCState *env)
diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
index 11bf275..e5d59a7 100644
--- a/target-openrisc/machine.c
+++ b/target-openrisc/machine.c
@@ -20,11 +20,31 @@
#include "hw/hw.h"
#include "hw/boards.h"
+static const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = CPU_SAVE_VERSION,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32),
+ VMSTATE_UINT32(sr, CPUOpenRISCState),
+ VMSTATE_UINT32(epcr, CPUOpenRISCState),
+ VMSTATE_UINT32(eear, CPUOpenRISCState),
+ VMSTATE_UINT32(esr, CPUOpenRISCState),
+ VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
+ VMSTATE_UINT32(pc, CPUOpenRISCState),
+ VMSTATE_UINT32(npc, CPUOpenRISCState),
+ VMSTATE_UINT32(ppc, CPUOpenRISCState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
void cpu_save(QEMUFile *f, void *opaque)
{
+ vmstate_save_state(f, &vmstate_cpu, opaque);
}
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
- return 0;
+ return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
}
--
1.7.9.5
- [Qemu-devel] [PATCH v4 00/16] QEMU OpenRISC support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 01/16] target-or32: Add target stubs and cpu support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 02/16] target-or32: Add target machine,
Jia Liu <=
- [Qemu-devel] [PATCH v4 03/16] target-or32: Add MMU support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 04/16] target-or32: Add interrupt support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 05/16] target-or32: Add exception support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 06/16] target-or32: Add int instruction helpers, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 09/16] target-or32: Add PIC support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 10/16] target-or32: Add timer support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 11/16] target-or32: Add a IIS dummy board, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 13/16] target-or32: Add gdb stub support, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 14/16] target-or32: Add linux syscall, signal and termbits, Jia Liu, 2012/06/11
- [Qemu-devel] [PATCH v4 15/16] target-or32: Add linux user support, Jia Liu, 2012/06/11