Re: [Qemu-devel] [PATCH] MIPS: Correct FCR0 initialization

[Richard Henderson]

On 2012-06-07 18:04, Maciej W. Rozycki wrote:
>  I have verified this change with system emulation running the GDB test 
> suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), 
> there were 55 progressions and no regressions.
> 
> Signed-off-by: Maciej W. Rozycki <address@hidden>
> ---
> 
>  Sent on behalf of Nathan, who's since left the company.  Please apply.
> 
>   Maciej
> 
> qemu-mips-fcr0.diff
> Index: qemu-git-trunk/target-mips/translate.c
> ===================================================================
> --- qemu-git-trunk.orig/target-mips/translate.c       2012-06-04 
> 05:35:53.245610241 +0100
> +++ qemu-git-trunk/target-mips/translate.c    2012-06-04 05:39:26.245563823 
> +0100
> @@ -12776,6 +12776,7 @@ void cpu_state_reset(CPUMIPSState *env)
>      env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3;
>      env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask;
>      env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4;
> +    env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;

Reviewed-by: Richard Henderson <address@hidden>


r~