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[Qemu-devel] [PATCH 31/33] target-arm: Move block cache ops to new cp15
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 31/33] target-arm: Move block cache ops to new cp15 framework |
Date: |
Wed, 20 Jun 2012 13:27:19 +0100 |
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 13 +++++++++++++
target-arm/translate.c | 7 +------
2 files changed, 14 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9b28f6b..10d4635 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -810,6 +810,19 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
/* We never have a a block transfer operation in progress */
{ .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* The cache ops themselves: these all NOP for QEMU */
+ { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
+ .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
+ .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
+ .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
+ .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
REGINFO_SENTINEL
};
diff --git a/target-arm/translate.c b/target-arm/translate.c
index f4e9435..fcdc9d3 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2451,12 +2451,7 @@ static int disas_cp15_insn(CPUARMState *env,
DisasContext *s, uint32_t insn)
return 1;
if ((insn & (1 << 25)) == 0) {
- if (insn & (1 << 20)) {
- /* mrrc */
- return 1;
- }
- /* mcrr. Used for block cache operations, so implement as no-op. */
- return 0;
+ return 1;
}
if ((insn & (1 << 4)) == 0) {
/* cdp */
--
1.7.1
- [Qemu-devel] [PULL 00/33] target-arm queue, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 13/33] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 10/33] target-arm: Convert WFI/barriers special cases to cp_reginfo, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 14/33] target-arm: Convert cp15 c3 register, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 32/33] target-arm: Remove remaining old cp15 infrastructure, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 09/33] target-arm: Convert TEECR, TEEHBR to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 03/33] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 31/33] target-arm: Move block cache ops to new cp15 framework,
Peter Maydell <=
- [Qemu-devel] [PATCH 22/33] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 08/33] target-arm: Convert debug registers to cp_reginfo, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 30/33] target-arm: Remove c0_cachetype CPUARMState field, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 02/33] target-arm: initial coprocessor register framework, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 28/33] target-arm: Convert MPIDR, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 16/33] target-arm: Convert cp15 crn=2 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 19/33] target-arm: Convert cp15 crn=15 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 04/33] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 20/33] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/06/20