Re: [Qemu-devel] [PATCH v5 00/16] QEMU OpenRISC support

[Blue Swirl]

On Wed, Jun 20, 2012 at 7:10 AM, Jia Liu <address@hidden> wrote:
> Hi Blue,
>
> On Tue, Jun 19, 2012 at 3:11 AM, Blue Swirl <address@hidden> wrote:
>> On Mon, Jun 18, 2012 at 1:02 AM, Jia Liu <address@hidden> wrote:
>>> This is the OpenCores OpenRISC 1200 support for QEMU.
>>> Full implementation of the system-model and linux-user-model support.
>>>
>>> OpenRISC 1200 is a OpenCores open source CPU,
>>> its architecture manual can be found at
>>> http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf
>>>
>>> A OpenRISC Linux kernel contain initramfs for qemu-system-or32 testing
>>> can be found at
>>> https://docs.google.com/file/d/0BxeTrz3x0CBLSjR3Sk5Vd3h1eDA/edit?pli=1
>>>
>>> A OpenRISC hello-world program for qemu-or32 testing can be found at
>>> https://docs.google.com/file/d/0BxeTrz3x0CBLN3RSWUFNYktrU2M/edit?pli=1
>>>
>>> Signed-off-by: Jia Liu <address@hidden>
>>
>> I had minor comments to a few patches, others looked ready. Please
>> still check the patches with scripts/checkpatch.pl.
>>
>
> I've checked the patches with scripts/checkpatch.pl.
>
> when I run "./scripts/checkpatch.pl *.patch", it is all OK,
>
> but when I run "./scripts/checkpatch.pl 0012-xxx.patch", 0006 and 0012
> have ERROR like this:
>
> ERROR: need consistent spacing around '*' (ctx:WxV)
> #99: FILE: target-openrisc/int_helper.c:53:
> +target_ulong HELPER(mul32)(CPUOpenRISCState *env,
>
> It is really weird. And, I don't know how to handle it.

It's a limitation in checkpatch.pl, it is confused by any CPUxxxState
for some reason. Please just ignore these cases.

>
>
>>> ---
>>>
>>> Version History:
>>> V5:
>>> Addressed Blue's review comments:
>>> - reimplement l.mul* l.mfspr l.add* l.sub* and more.
>>> - shoot bugs with "--enable-debug-tcg"
>>>
>>> V4:
>>> Addressed Max's review comments:
>>> - fix l.div l.mac* l.mul*, and more.
>>>
>>> Addressed Richard, Wei-Ren and Andreas's review comments:
>>> - replace tcg_temp_new_i32 with tcg_temp_local_new_i32 in l.div translation.
>>>
>>> Addressed Andreas's review comments:
>>> - update to suit Makefile system.
>>>
>>> - add UPR CPUCFGR and MMUCFGR impelement.
>>> - add instruction check functions.
>>>
>>> Version History:
>>> V3:
>>> Addressed Stefan and Andreas's review comments:
>>> - use QEMU and OpenRISC's official name.
>>>
>>> Addressed Andreas's review comments:
>>> - reimplement cpu QOM.
>>> - combine target stubs and QOM implement.
>>> - use new commit message and subject.
>>>
>>> Addressed Max's review comments:
>>> - handle div zero exception.
>>> - reimplement float point instructions.
>>> - fix l.mac*, l.mul*, and more.
>>>
>>> V2:
>>> Addressed Malc, Weiren, Andreas and Blue's review comments:
>>> - reimplement cpu QOM.
>>>
>>> Addressed Andreas's review comments:
>>> - reimplement machine.
>>> - rewrite the Copyright Notice using better format.
>>>
>>> Addressed Blue and Weiren's review comments:
>>> - compiling with AREG0 and remove global env, no dyngen-exe longer.
>>>
>>> Addressed Max, Blue and Weiren's review comments:
>>> - handle div zero exception.
>>> - handle illegal instruction.
>>>
>>> Addressed Blue's review comments:
>>> - separate do_interrupt into intrpt.c form intrpt_helper.c.
>>> - add QEMU_NORETURN to raise_exception.
>>> - reimplement float instrutions.
>>> - fix type of linux syscall and termbits.
>>> - reimplement sim board.
>>> - use the LGPL web URL in Copyright Notice.
>>> - reimplemt branch instructions.
>>>
>>> - split taregt stubs, QOM and machine.
>>>
>>> V1:
>>> - add QEMU OpenRISC support.
>>> - well tested on x64 machine, and final tested x86 machine.
>>>
>>> Jia Liu (16):
>>>  target-or32: Add target stubs and cpu support
>>>  target-or32: Add target machine
>>>  target-or32: Add MMU support
>>>  target-or32: Add interrupt support
>>>  target-or32: Add exception support
>>>  target-or32: Add int instruction helpers
>>>  target-or32: Add float instruction helpers
>>>  target-or32: Add translation routines
>>>  target-or32: Add PIC support
>>>  target-or32: Add timer support
>>>  target-or32: Add a IIS dummy board
>>>  target-or32: Add system instructions
>>>  target-or32: Add gdb stub support
>>>  target-or32: Add linux syscall, signal and termbits
>>>  target-or32: Add linux user support
>>>  target-or32: Add testcases
>>>
>>>  arch_init.c                         |    2 +
>>>  arch_init.h                         |    1 +
>>>  configure                           |   15 +-
>>>  cpu-exec.c                          |   19 +
>>>  default-configs/or32-linux-user.mak |    2 +
>>>  default-configs/or32-softmmu.mak    |    6 +
>>>  elf.h                               |    2 +
>>>  gdbstub.c                           |   64 ++
>>>  hw/openrisc/Makefile.objs           |    3 +
>>>  hw/openrisc_cpudev.h                |   29 +
>>>  hw/openrisc_pic.c                   |   78 ++
>>>  hw/openrisc_sim.c                   |  145 +++
>>>  hw/openrisc_timer.c                 |  160 +++
>>>  linux-user/elfload.c                |   41 +
>>>  linux-user/main.c                   |  100 ++
>>>  linux-user/openrisc/syscall.h       |   24 +
>>>  linux-user/openrisc/syscall_nr.h    |  506 +++++++++
>>>  linux-user/openrisc/target_signal.h |   26 +
>>>  linux-user/openrisc/termbits.h      |  294 +++++
>>>  linux-user/signal.c                 |  229 ++++
>>>  linux-user/syscall.c                |    2 +-
>>>  linux-user/syscall_defs.h           |   40 +-
>>>  poison.h                            |    1 +
>>>  target-openrisc/Makefile.objs       |    4 +
>>>  target-openrisc/cpu.c               |  240 +++++
>>>  target-openrisc/cpu.h               |  445 ++++++++
>>>  target-openrisc/excp.c              |   27 +
>>>  target-openrisc/excp.h              |   28 +
>>>  target-openrisc/excp_helper.c       |   27 +
>>>  target-openrisc/fpu_helper.c        |  275 +++++
>>>  target-openrisc/helper.h            |   69 ++
>>>  target-openrisc/int_helper.c        |   51 +
>>>  target-openrisc/intrpt.c            |   74 ++
>>>  target-openrisc/intrpt_helper.c     |   52 +
>>>  target-openrisc/machine.c           |   50 +
>>>  target-openrisc/mmu.c               |  236 ++++
>>>  target-openrisc/mmu_helper.c        |   63 ++
>>>  target-openrisc/sys_helper.c        |  233 ++++
>>>  target-openrisc/translate.c         | 2036 
>>> +++++++++++++++++++++++++++++++++++
>>>  tests/tcg/openrisc/Makefile         |   71 ++
>>>  tests/tcg/openrisc/test_add.c       |   34 +
>>>  tests/tcg/openrisc/test_addc.c      |   39 +
>>>  tests/tcg/openrisc/test_addi.c      |   31 +
>>>  tests/tcg/openrisc/test_addic.c     |   33 +
>>>  tests/tcg/openrisc/test_and_or.c    |   61 ++
>>>  tests/tcg/openrisc/test_bf.c        |   46 +
>>>  tests/tcg/openrisc/test_bnf.c       |   50 +
>>>  tests/tcg/openrisc/test_div.c       |   32 +
>>>  tests/tcg/openrisc/test_divu.c      |   32 +
>>>  tests/tcg/openrisc/test_extx.c      |   72 ++
>>>  tests/tcg/openrisc/test_fx.c        |   53 +
>>>  tests/tcg/openrisc/test_j.c         |   26 +
>>>  tests/tcg/openrisc/test_jal.c       |   26 +
>>>  tests/tcg/openrisc/test_lf_add.c    |   39 +
>>>  tests/tcg/openrisc/test_lf_div.c    |   34 +
>>>  tests/tcg/openrisc/test_lf_eqs.c    |   84 ++
>>>  tests/tcg/openrisc/test_lf_ges.c    |   84 ++
>>>  tests/tcg/openrisc/test_lf_gts.c    |   84 ++
>>>  tests/tcg/openrisc/test_lf_les.c    |   84 ++
>>>  tests/tcg/openrisc/test_lf_lts.c    |   91 ++
>>>  tests/tcg/openrisc/test_lf_mul.c    |   22 +
>>>  tests/tcg/openrisc/test_lf_nes.c    |   87 ++
>>>  tests/tcg/openrisc/test_lf_rem.c    |   32 +
>>>  tests/tcg/openrisc/test_lf_sub.c    |   33 +
>>>  tests/tcg/openrisc/test_logic.c     |  100 ++
>>>  tests/tcg/openrisc/test_lx.c        |   78 ++
>>>  tests/tcg/openrisc/test_movhi.c     |   30 +
>>>  tests/tcg/openrisc/test_mul.c       |   47 +
>>>  tests/tcg/openrisc/test_muli.c      |   47 +
>>>  tests/tcg/openrisc/test_mulu.c      |   47 +
>>>  tests/tcg/openrisc/test_sfeq.c      |   44 +
>>>  tests/tcg/openrisc/test_sfeqi.c     |   39 +
>>>  tests/tcg/openrisc/test_sfges.c     |   44 +
>>>  tests/tcg/openrisc/test_sfgesi.c    |   40 +
>>>  tests/tcg/openrisc/test_sfgeu.c     |   44 +
>>>  tests/tcg/openrisc/test_sfgeui.c    |   41 +
>>>  tests/tcg/openrisc/test_sfgts.c     |   45 +
>>>  tests/tcg/openrisc/test_sfgtsi.c    |   41 +
>>>  tests/tcg/openrisc/test_sfgtu.c     |   43 +
>>>  tests/tcg/openrisc/test_sfgtui.c    |   42 +
>>>  tests/tcg/openrisc/test_sfles.c     |   26 +
>>>  tests/tcg/openrisc/test_sflesi.c    |   39 +
>>>  tests/tcg/openrisc/test_sfleu.c     |   43 +
>>>  tests/tcg/openrisc/test_sfleui.c    |   39 +
>>>  tests/tcg/openrisc/test_sflts.c     |   43 +
>>>  tests/tcg/openrisc/test_sfltsi.c    |   38 +
>>>  tests/tcg/openrisc/test_sfltu.c     |   41 +
>>>  tests/tcg/openrisc/test_sfltui.c    |   39 +
>>>  tests/tcg/openrisc/test_sfne.c      |   43 +
>>>  tests/tcg/openrisc/test_sfnei.c     |   38 +
>>>  tests/tcg/openrisc/test_sub.c       |   34 +
>>>  91 files changed, 8168 insertions(+), 6 deletions(-)
>>>  create mode 100644 default-configs/or32-linux-user.mak
>>>  create mode 100644 default-configs/or32-softmmu.mak
>>>  create mode 100644 hw/openrisc/Makefile.objs
>>>  create mode 100644 hw/openrisc_cpudev.h
>>>  create mode 100644 hw/openrisc_pic.c
>>>  create mode 100644 hw/openrisc_sim.c
>>>  create mode 100644 hw/openrisc_timer.c
>>>  create mode 100644 linux-user/openrisc/syscall.h
>>>  create mode 100644 linux-user/openrisc/syscall_nr.h
>>>  create mode 100644 linux-user/openrisc/target_signal.h
>>>  create mode 100644 linux-user/openrisc/termbits.h
>>>  create mode 100644 target-openrisc/Makefile.objs
>>>  create mode 100644 target-openrisc/cpu.c
>>>  create mode 100644 target-openrisc/cpu.h
>>>  create mode 100644 target-openrisc/excp.c
>>>  create mode 100644 target-openrisc/excp.h
>>>  create mode 100644 target-openrisc/excp_helper.c
>>>  create mode 100644 target-openrisc/fpu_helper.c
>>>  create mode 100644 target-openrisc/helper.h
>>>  create mode 100644 target-openrisc/int_helper.c
>>>  create mode 100644 target-openrisc/intrpt.c
>>>  create mode 100644 target-openrisc/intrpt_helper.c
>>>  create mode 100644 target-openrisc/machine.c
>>>  create mode 100644 target-openrisc/mmu.c
>>>  create mode 100644 target-openrisc/mmu_helper.c
>>>  create mode 100644 target-openrisc/sys_helper.c
>>>  create mode 100644 target-openrisc/translate.c
>>>  create mode 100644 tests/tcg/openrisc/Makefile
>>>  create mode 100644 tests/tcg/openrisc/test_add.c
>>>  create mode 100644 tests/tcg/openrisc/test_addc.c
>>>  create mode 100644 tests/tcg/openrisc/test_addi.c
>>>  create mode 100644 tests/tcg/openrisc/test_addic.c
>>>  create mode 100644 tests/tcg/openrisc/test_and_or.c
>>>  create mode 100644 tests/tcg/openrisc/test_bf.c
>>>  create mode 100644 tests/tcg/openrisc/test_bnf.c
>>>  create mode 100644 tests/tcg/openrisc/test_div.c
>>>  create mode 100644 tests/tcg/openrisc/test_divu.c
>>>  create mode 100644 tests/tcg/openrisc/test_extx.c
>>>  create mode 100644 tests/tcg/openrisc/test_fx.c
>>>  create mode 100644 tests/tcg/openrisc/test_j.c
>>>  create mode 100644 tests/tcg/openrisc/test_jal.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_add.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_div.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_eqs.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_ges.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_gts.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_les.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_lts.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_mul.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_nes.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_rem.c
>>>  create mode 100644 tests/tcg/openrisc/test_lf_sub.c
>>>  create mode 100644 tests/tcg/openrisc/test_logic.c
>>>  create mode 100644 tests/tcg/openrisc/test_lx.c
>>>  create mode 100644 tests/tcg/openrisc/test_movhi.c
>>>  create mode 100644 tests/tcg/openrisc/test_mul.c
>>>  create mode 100644 tests/tcg/openrisc/test_muli.c
>>>  create mode 100644 tests/tcg/openrisc/test_mulu.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfeq.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfeqi.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfges.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfgesi.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfgeu.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfgeui.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfgts.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfgtsi.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfgtu.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfgtui.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfles.c
>>>  create mode 100644 tests/tcg/openrisc/test_sflesi.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfleu.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfleui.c
>>>  create mode 100644 tests/tcg/openrisc/test_sflts.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfltsi.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfltu.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfltui.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfne.c
>>>  create mode 100644 tests/tcg/openrisc/test_sfnei.c
>>>  create mode 100644 tests/tcg/openrisc/test_sub.c
>>>
>>> --
>>> 1.7.9.5
>>>
>>>
>
>
> Regards,
> Jia.