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[Qemu-devel] [PATCH 59/72] PPC: e500: Extend address/size of / to 64bit
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 59/72] PPC: e500: Extend address/size of / to 64bit |
Date: |
Sun, 24 Jun 2012 01:07:23 +0200 |
We want to be able to support >= 4GB of RAM. To do so, we need to be able
to tell the guest OS how much RAM it has.
However, that information today is capped to 32bit. So let's extend the
offset and size fields to 64bit, so we can fit in big addresses and even
one day - if we wish to do so - map devices above 32bit.
Signed-off-by: Alexander Graf <address@hidden>
---
hw/ppce500_mpc8544ds.c | 28 ++++++++++++++++++----------
1 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index c6a09bb..bf48bc7 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -90,7 +90,7 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
const char *kernel_cmdline)
{
int ret = -1;
- uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
+ uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
int fdt_size;
void *fdt;
uint8_t hypercall[16];
@@ -108,9 +108,16 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
char gutil[128];
char pci[128];
uint32_t pci_map[9 * 8];
- uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0,
- 0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000,
- 0x0, 0x10000 };
+ uint32_t pci_ranges[14] =
+ {
+ 0x2000000, 0x0, 0xc0000000,
+ 0x0, 0xc0000000,
+ 0x0, 0x20000000,
+
+ 0x1000000, 0x0, 0x0,
+ 0x0, 0xe1000000,
+ 0x0, 0x10000,
+ };
QemuOpts *machine_opts;
const char *dumpdtb = NULL;
const char *dtb_file = NULL;
@@ -144,8 +151,8 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_string(fdt, "/", "model", model);
qemu_devtree_setprop(fdt, "/", "compatible", compatible,
sizeof(compatible));
- qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1);
- qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1);
+ qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2);
+ qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2);
qemu_devtree_add_subnode(fdt, "/memory");
qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
@@ -239,7 +246,8 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
sizeof(compatible_sb));
qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
- qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE,
+ qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0,
+ MPC8544_CCSRBAR_BASE >> 32,
MPC8544_CCSRBAR_BASE,
MPC8544_CCSRBAR_SIZE);
/* XXX should contain a reasonable value */
qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
@@ -313,12 +321,12 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2, 0, 0);
qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
- for (i = 0; i < 12; i++) {
+ for (i = 0; i < 14; i++) {
pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
}
qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
- qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE,
- 0x1000);
+ qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
+ MPC8544_PCI_REGS_BASE, 0, 0x1000);
qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
--
1.6.0.2
- [Qemu-devel] [PATCH 64/72] uImage: increase the gzip load size, (continued)
- [Qemu-devel] [PATCH 64/72] uImage: increase the gzip load size, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 65/72] PPC: Add some booke SPR defines, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 52/72] PPC: e500: dt: use 64bit cell helper, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 66/72] PPC: Add support for MSR_CM, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 62/72] dt: make setprop argument static, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 72/72] PPC: BookE206: Bump MAS2 to 64bit, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 69/72] PPC: Add e5500 CPU target, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 67/72] PPC: BookE: Implement EPR SPR, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 48/72] PPC: e500: dt: create global-utils node dynamically, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 71/72] PPC: BookE: Support 32 and 64 bit wide MAS2, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 59/72] PPC: e500: Extend address/size of / to 64bit,
Alexander Graf <=
- [Qemu-devel] [PATCH 56/72] PPC: e500: Use new MPIC dt format, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 53/72] PPC: e500: dt: use target_phys_addr_t for ramsize, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 54/72] PPC: e500: enable manual loading of dtb blob, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 49/72] PPC: e500: dt: create pci node dynamically, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 51/72] dt: Add -machine dumpdtb option to dump the current dtb, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 55/72] Revert "dt: temporarily disable subtree creation failure check", Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 70/72] PPC: Extract SPR dump generation into its own function, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 50/72] PPC: e500: dt: start with empty device tree, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 68/72] PPC: BookE: Make ivpr selectable by CPU type, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 57/72] PPC: e500: Use new SOC dt format, Alexander Graf, 2012/06/23