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[Qemu-devel] [PATCH 07/13] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 regi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 07/13] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers |
Date: |
Thu, 28 Jun 2012 15:36:00 +0100 |
Add implementations of the AMAIR0 and AMAIR1 LPAE
Auxiliary Memory Attribute Indirection Registers.
These are implementation defined and we choose to
implement them as RAZ/WI, matching the Cortex-A7
and Cortex-A15.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 16 ++++++++++++++++
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ef0b1d..3ee0555 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -871,6 +871,19 @@ static const ARMCPRegInfo mpidr_cp_reginfo[] = {
REGINFO_SENTINEL
};
+static const ARMCPRegInfo lpae_cp_reginfo[] = {
+ /* NOP AMAIR0/1: the override is because these clash with tha rather
+ * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
+ */
+ { .name = "AMAIR0", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
+ .resetvalue = 0 },
+ { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
+ .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
+ .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
value)
{
env->cp15.c1_sys = value;
@@ -1016,6 +1029,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_MPIDR)) {
define_arm_cp_regs(cpu, mpidr_cp_reginfo);
}
+ if (arm_feature(env, ARM_FEATURE_LPAE)) {
+ define_arm_cp_regs(cpu, lpae_cp_reginfo);
+ }
/* Slightly awkwardly, the OMAP and StrongARM cores need all of
* cp15 crn=0 to be writes-ignored, whereas for other cores they should
* be read-only (ie write causes UNDEF exception).
--
1.7.1
- [Qemu-devel] [PATCH 00/13] ARM: Add LPAE support, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 10/13] target-arm: Use target_phys_addr_t in get_phys_addr(), Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 02/13] target-arm: Fix typo that meant TTBR1 accesses went to TTBR0, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 09/13] target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 07/13] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers,
Peter Maydell <=
- [Qemu-devel] [PATCH 04/13] ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 08/13] target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 12/13] target-arm: Implement TTBCR changes for LPAE, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 03/13] bitops.h: Add functions to extract and deposit bitfields, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 05/13] target-arm: Implement privileged-execute-never (PXN), Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 11/13] target-arm: Implement long-descriptor PAR format, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 01/13] hw/cadence_gem: Make rx_desc_addr and tx_desc_addr uint32_t, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 13/13] target-arm: Add support for long format translation table walks, Peter Maydell, 2012/06/28
- [Qemu-devel] [PATCH 06/13] target-arm: Extend feature flags to 64 bits, Peter Maydell, 2012/06/28