From b508a4368c9a315e4905c1fccbca00971be80ab4 Mon Sep 17 00:00:00 2001 Message-Id: In-Reply-To: References: From: Blue Swirl Date: Sun, 29 Apr 2012 18:42:47 +0000 Subject: [PATCH 21/25] x86: avoid AREG0 for misc helpers Add an explicit CPUX86State parameter instead of relying on AREG0. Signed-off-by: Blue Swirl --- Makefile.target | 1 - target-i386/helper.h | 40 +++++++++++++------------- target-i386/misc_helper.c | 69 ++++++++++++++++++++++----------------------- target-i386/translate.c | 49 ++++++++++++++++++------------- 4 files changed, 82 insertions(+), 77 deletions(-) diff --git a/Makefile.target b/Makefile.target index a87b9cc..ea55b37 100644 --- a/Makefile.target +++ b/Makefile.target @@ -93,7 +93,6 @@ endif ifeq ($(TARGET_BASE_ARCH), i386) libobj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o libobj-y += svm_helper.o smm_helper.o misc_helper.o -misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) endif libobj-$(TARGET_SPARC64) += vis_helper.o libobj-$(CONFIG_NEED_MMU) += mmu.o diff --git a/target-i386/helper.h b/target-i386/helper.h index ec7edca..9a9c064 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -41,12 +41,12 @@ DEF_HELPER_4(lcall_protected, void, int, tl, int, int) DEF_HELPER_1(iret_real, void, int) DEF_HELPER_2(iret_protected, void, int, int) DEF_HELPER_2(lret_protected, void, int, int) -DEF_HELPER_1(read_crN, tl, int) -DEF_HELPER_2(write_crN, void, int, tl) -DEF_HELPER_1(lmsw, void, tl) +DEF_HELPER_2(read_crN, tl, env, int) +DEF_HELPER_3(write_crN, void, env, int, tl) +DEF_HELPER_2(lmsw, void, env, tl) DEF_HELPER_1(clts, void, env) -DEF_HELPER_2(movl_drN_T0, void, int, tl) -DEF_HELPER_1(invlpg, void, tl) +DEF_HELPER_3(movl_drN_T0, void, env, int, tl) +DEF_HELPER_2(invlpg, void, env, tl) DEF_HELPER_3(enter_level, void, int, int, tl) #ifdef TARGET_X86_64 @@ -58,10 +58,10 @@ DEF_HELPER_1(sysexit, void, int) DEF_HELPER_1(syscall, void, int) DEF_HELPER_1(sysret, void, int) #endif -DEF_HELPER_1(hlt, void, int) -DEF_HELPER_1(monitor, void, tl) -DEF_HELPER_1(mwait, void, int) -DEF_HELPER_0(debug, void) +DEF_HELPER_2(hlt, void, env, int) +DEF_HELPER_2(monitor, void, env, tl) +DEF_HELPER_2(mwait, void, env, int) +DEF_HELPER_1(debug, void, env) DEF_HELPER_1(reset_rf, void, env) DEF_HELPER_3(raise_interrupt, void, env, int, int) DEF_HELPER_2(raise_exception, void, env, int) @@ -72,22 +72,22 @@ DEF_HELPER_1(reset_inhibit_irq, void, env) DEF_HELPER_2(boundw, void, tl, int) DEF_HELPER_2(boundl, void, tl, int) DEF_HELPER_1(rsm, void, env) -DEF_HELPER_1(into, void, int) +DEF_HELPER_2(into, void, env, int) DEF_HELPER_1(cmpxchg8b, void, tl) #ifdef TARGET_X86_64 DEF_HELPER_1(cmpxchg16b, void, tl) #endif -DEF_HELPER_0(single_step, void) -DEF_HELPER_0(cpuid, void) -DEF_HELPER_0(rdtsc, void) -DEF_HELPER_0(rdtscp, void) -DEF_HELPER_0(rdpmc, void) -DEF_HELPER_0(rdmsr, void) -DEF_HELPER_0(wrmsr, void) +DEF_HELPER_1(single_step, void, env) +DEF_HELPER_1(cpuid, void, env) +DEF_HELPER_1(rdtsc, void, env) +DEF_HELPER_1(rdtscp, void, env) +DEF_HELPER_1(rdpmc, void, env) +DEF_HELPER_1(rdmsr, void, env) +DEF_HELPER_1(wrmsr, void, env) -DEF_HELPER_1(check_iob, void, i32) -DEF_HELPER_1(check_iow, void, i32) -DEF_HELPER_1(check_iol, void, i32) +DEF_HELPER_2(check_iob, void, env, i32) +DEF_HELPER_2(check_iow, void, env, i32) +DEF_HELPER_2(check_iol, void, env, i32) DEF_HELPER_2(outb, void, i32, i32) DEF_HELPER_1(inb, tl, i32) DEF_HELPER_2(outw, void, i32, i32) diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c index 0cb27a9..dbecb4b 100644 --- a/target-i386/misc_helper.c +++ b/target-i386/misc_helper.c @@ -18,12 +18,11 @@ */ #include "cpu.h" -#include "dyngen-exec.h" #include "ioport.h" #include "helper.h" /* check if Port I/O is allowed in TSS */ -static inline void check_io(int addr, int size) +static inline void check_io(CPUX86State *env, int addr, int size) { int io_offset, val, mask; @@ -49,19 +48,19 @@ static inline void check_io(int addr, int size) } } -void helper_check_iob(uint32_t t0) +void helper_check_iob(CPUX86State *env, uint32_t t0) { - check_io(t0, 1); + check_io(env, t0, 1); } -void helper_check_iow(uint32_t t0) +void helper_check_iow(CPUX86State *env, uint32_t t0) { - check_io(t0, 2); + check_io(env, t0, 2); } -void helper_check_iol(uint32_t t0) +void helper_check_iol(CPUX86State *env, uint32_t t0) { - check_io(t0, 4); + check_io(env, t0, 4); } void helper_outb(uint32_t port, uint32_t data) @@ -94,7 +93,7 @@ target_ulong helper_inl(uint32_t port) return cpu_inl(port); } -void helper_into(int next_eip_addend) +void helper_into(CPUX86State *env, int next_eip_addend) { int eflags; @@ -104,7 +103,7 @@ void helper_into(int next_eip_addend) } } -void helper_single_step(void) +void helper_single_step(CPUX86State *env) { #ifndef CONFIG_USER_ONLY check_hw_breakpoints(env, 1); @@ -113,7 +112,7 @@ void helper_single_step(void) raise_exception(env, EXCP01_DB); } -void helper_cpuid(void) +void helper_cpuid(CPUX86State *env) { uint32_t eax, ebx, ecx, edx; @@ -127,20 +126,20 @@ void helper_cpuid(void) } #if defined(CONFIG_USER_ONLY) -target_ulong helper_read_crN(int reg) +target_ulong helper_read_crN(CPUX86State *env, int reg) { return 0; } -void helper_write_crN(int reg, target_ulong t0) +void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { } -void helper_movl_drN_T0(int reg, target_ulong t0) +void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) { } #else -target_ulong helper_read_crN(int reg) +target_ulong helper_read_crN(CPUX86State *env, int reg) { target_ulong val; @@ -160,7 +159,7 @@ target_ulong helper_read_crN(int reg) return val; } -void helper_write_crN(int reg, target_ulong t0) +void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) { cpu_svm_check_intercept_param(env, SVM_EXIT_WRITE_CR0 + reg, 0); switch (reg) { @@ -185,7 +184,7 @@ void helper_write_crN(int reg, target_ulong t0) } } -void helper_movl_drN_T0(int reg, target_ulong t0) +void helper_movl_drN_T0(CPUX86State *env, int reg, target_ulong t0) { int i; @@ -207,21 +206,21 @@ void helper_movl_drN_T0(int reg, target_ulong t0) } #endif -void helper_lmsw(target_ulong t0) +void helper_lmsw(CPUX86State *env, target_ulong t0) { /* only 4 lower bits of CR0 are modified. PE cannot be set to zero if already set to one. */ t0 = (env->cr[0] & ~0xe) | (t0 & 0xf); - helper_write_crN(0, t0); + helper_write_crN(env, 0, t0); } -void helper_invlpg(target_ulong addr) +void helper_invlpg(CPUX86State *env, target_ulong addr) { cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0); tlb_flush_page(env, addr); } -void helper_rdtsc(void) +void helper_rdtsc(CPUX86State *env) { uint64_t val; @@ -235,13 +234,13 @@ void helper_rdtsc(void) EDX = (uint32_t)(val >> 32); } -void helper_rdtscp(void) +void helper_rdtscp(CPUX86State *env) { - helper_rdtsc(); + helper_rdtsc(env); ECX = (uint32_t)(env->tsc_aux); } -void helper_rdpmc(void) +void helper_rdpmc(CPUX86State *env) { if ((env->cr[4] & CR4_PCE_MASK) && ((env->hflags & HF_CPL_MASK) != 0)) { raise_exception(env, EXCP0D_GPF); @@ -253,15 +252,15 @@ void helper_rdpmc(void) } #if defined(CONFIG_USER_ONLY) -void helper_wrmsr(void) +void helper_wrmsr(CPUX86State *env) { } -void helper_rdmsr(void) +void helper_rdmsr(CPUX86State *env) { } #else -void helper_wrmsr(void) +void helper_wrmsr(CPUX86State *env) { uint64_t val; @@ -408,7 +407,7 @@ void helper_wrmsr(void) } } -void helper_rdmsr(void) +void helper_rdmsr(CPUX86State *env) { uint64_t val; @@ -549,7 +548,7 @@ void helper_rdmsr(void) } #endif -static void do_hlt(void) +static void do_hlt(CPUX86State *env) { env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */ env->halted = 1; @@ -557,15 +556,15 @@ static void do_hlt(void) cpu_loop_exit(env); } -void helper_hlt(int next_eip_addend) +void helper_hlt(CPUX86State *env, int next_eip_addend) { cpu_svm_check_intercept_param(env, SVM_EXIT_HLT, 0); EIP += next_eip_addend; - do_hlt(); + do_hlt(env); } -void helper_monitor(target_ulong ptr) +void helper_monitor(CPUX86State *env, target_ulong ptr) { if ((uint32_t)ECX != 0) { raise_exception(env, EXCP0D_GPF); @@ -574,7 +573,7 @@ void helper_monitor(target_ulong ptr) cpu_svm_check_intercept_param(env, SVM_EXIT_MONITOR, 0); } -void helper_mwait(int next_eip_addend) +void helper_mwait(CPUX86State *env, int next_eip_addend) { if ((uint32_t)ECX != 0) { raise_exception(env, EXCP0D_GPF); @@ -587,11 +586,11 @@ void helper_mwait(int next_eip_addend) /* more than one CPU: do not sleep because another CPU may wake this one */ } else { - do_hlt(); + do_hlt(env); } } -void helper_debug(void) +void helper_debug(CPUX86State *env) { env->exception_index = EXCP_DEBUG; cpu_loop_exit(env); diff --git a/target-i386/translate.c b/target-i386/translate.c index 2ea52ca..2fece4e 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -730,9 +730,15 @@ static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip, state_saved = 1; tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); switch (ot) { - case 0: gen_helper_check_iob(cpu_tmp2_i32); break; - case 1: gen_helper_check_iow(cpu_tmp2_i32); break; - case 2: gen_helper_check_iol(cpu_tmp2_i32); break; + case 0: + gen_helper_check_iob(cpu_env, cpu_tmp2_i32); + break; + case 1: + gen_helper_check_iow(cpu_env, cpu_tmp2_i32); + break; + case 2: + gen_helper_check_iol(cpu_env, cpu_tmp2_i32); + break; } } if(s->flags & HF_SVMI_MASK) { @@ -2726,7 +2732,7 @@ static void gen_debug(DisasContext *s, target_ulong cur_eip) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(cur_eip); - gen_helper_debug(); + gen_helper_debug(cpu_env); s->is_jmp = DISAS_TB_JUMP; } @@ -2743,9 +2749,9 @@ static void gen_eob(DisasContext *s) gen_helper_reset_rf(cpu_env); } if (s->singlestep_enabled) { - gen_helper_debug(); + gen_helper_debug(cpu_env); } else if (s->tf) { - gen_helper_single_step(); + gen_helper_single_step(cpu_env); } else { tcg_gen_exit_tb(0); } @@ -6811,7 +6817,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_into(tcg_const_i32(s->pc - pc_start)); + gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ @@ -6968,9 +6974,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); if (b & 2) { - gen_helper_rdmsr(); + gen_helper_rdmsr(cpu_env); } else { - gen_helper_wrmsr(); + gen_helper_wrmsr(cpu_env); } } break; @@ -6980,7 +6986,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (use_icount) gen_io_start(); - gen_helper_rdtsc(); + gen_helper_rdtsc(cpu_env); if (use_icount) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); @@ -6990,7 +6996,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_rdpmc(); + gen_helper_rdpmc(cpu_env); break; case 0x134: /* sysenter */ /* For Intel SYSENTER is valid on 64-bit */ @@ -7044,7 +7050,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_cpuid(); + gen_helper_cpuid(cpu_env); break; case 0xf4: /* hlt */ if (s->cpl != 0) { @@ -7053,7 +7059,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_helper_hlt(tcg_const_i32(s->pc - pc_start)); + gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); s->is_jmp = DISAS_TB_JUMP; } break; @@ -7165,7 +7171,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_andl_A0_ffff(); } gen_add_A0_ds_seg(s); - gen_helper_monitor(cpu_A0); + gen_helper_monitor(cpu_env, cpu_A0); break; case 1: /* mwait */ if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) || @@ -7173,7 +7179,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) goto illegal_op; gen_update_cc_op(s); gen_jmp_im(pc_start - s->cs_base); - gen_helper_mwait(tcg_const_i32(s->pc - pc_start)); + gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); gen_eob(s); break; default: @@ -7313,7 +7319,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); - gen_helper_lmsw(cpu_T[0]); + gen_helper_lmsw(cpu_env, cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -7327,7 +7333,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); gen_lea_modrm(s, modrm, ®_addr, &offset_addr); - gen_helper_invlpg(cpu_A0); + gen_helper_invlpg(cpu_env, cpu_A0); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } @@ -7362,7 +7368,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (use_icount) gen_io_start(); - gen_helper_rdtscp(); + gen_helper_rdtscp(cpu_env); if (use_icount) { gen_io_end(); gen_jmp(s, s->pc - s->cs_base); @@ -7544,11 +7550,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (b & 2) { gen_op_mov_TN_reg(ot, 0, rm); - gen_helper_write_crN(tcg_const_i32(reg), cpu_T[0]); + gen_helper_write_crN(cpu_env, tcg_const_i32(reg), + cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { - gen_helper_read_crN(cpu_T[0], tcg_const_i32(reg)); + gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg)); gen_op_mov_reg_T0(ot, rm); } break; @@ -7577,7 +7584,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (b & 2) { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg); gen_op_mov_TN_reg(ot, 0, rm); - gen_helper_movl_drN_T0(tcg_const_i32(reg), cpu_T[0]); + gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); } else { -- 1.7.2.5