Re: [Qemu-devel] [PATCH v2] x86: Fixed incorrect segment base address addition in 64-bits mode

[Max Filippov]

On Tue, Jul 3, 2012 at 2:20 AM, Vitaly Chipounov
<address@hidden> wrote:
> According to the Intel manual
> "Intel® 64 and IA-32 Architectures Software Developer’s Manual
> Volume 3", "3.4.4 Segment Loading Instructions in IA-32e Mode":
>
> "When in compatibility mode, FS and GS overrides operate as defined by
> 32-bit mode behavior regardless of the value loaded into the upper 32
> linear-address bits of the hidden descriptor register base field.
> Compatibility mode ignores the upper 32 bits when calculating an effective 
> address."
>
> However, the code misses the 64-bit mode case, where an instruction with
> address and segment size override would be translated incorrectly. For 
> example,
> inc dword ptr gs:260h[ebx*4] gets incorrectly translated to:
>
> (uint32_t)(gs.base + ebx * 4 + 0x260)
> instead of
> gs.base + (uint32_t)(ebx * 4 + 0x260)
>
> Signed-off-by: Vitaly Chipounov <address@hidden>

Reviewed-by: Max Filippov <address@hidden>

-- 
Thanks.
-- Max