[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 10/15] target-arm: Add 64 bit variants of DBGDRAR an
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 10/15] target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE |
Date: |
Thu, 12 Jul 2012 14:36:51 +0100 |
LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; we
only implement these as dummy RAZ versions; provide dummies for
the 64 bit accesses as well.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e96404a..0cf7b8d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -881,6 +881,11 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
{ .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
.resetvalue = 0 },
+ /* 64 bit access versions of the (dummy) debug registers */
+ { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
+ { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
REGINFO_SENTINEL
};
--
1.7.1
- [Qemu-devel] [PULL 00/15] target-arm queue, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 14/15] target-arm: Implement TTBCR changes for LPAE, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 04/15] target-arm: Fix TCG temp handling in 64 bit cp writes, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 07/15] target-arm: Implement privileged-execute-never (PXN), Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 09/15] target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 06/15] ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 10/15] target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE,
Peter Maydell <=
- [Qemu-devel] [PATCH 11/15] target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 15/15] target-arm: Add support for long format translation table walks, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 03/15] target-arm: Fix some copy-and-paste errors in cp register names, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 12/15] target-arm: Use target_phys_addr_t in get_phys_addr(), Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 01/15] target-arm: Fix CP15 based WFI, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 08/15] target-arm: Extend feature flags to 64 bits, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 02/15] target-arm: Fix typo that meant TTBR1 accesses went to TTBR0, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 13/15] target-arm: Implement long-descriptor PAR format, Peter Maydell, 2012/07/12
- [Qemu-devel] [PATCH 05/15] hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits, Peter Maydell, 2012/07/12
- Re: [Qemu-devel] [PULL 00/15] target-arm queue, Blue Swirl, 2012/07/14