[Qemu-devel] [PATCH v2 3/4] ARM: exynos4210_pmu: Introduced exynos4210_pmu_get_register_index

[Maksim Kozlov]

This patch just introduces exynos4210_pmu_get_register_index function
to get index of the register's value in the array on its offset. And
functions _read and _write were modified accordingly.

Signed-off-by: Maksim Kozlov <address@hidden>
---
 hw/exynos4210_pmu.c |   56 ++++++++++++++++++++++++++++++++------------------
 1 files changed, 36 insertions(+), 20 deletions(-)

diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c
index 26a726f..7f09c79 100644
--- a/hw/exynos4210_pmu.c
+++ b/hw/exynos4210_pmu.c
@@ -401,48 +401,64 @@ static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
 #define PMU_NUM_OF_REGISTERS \
     (sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg))
 
+#define PMU_UNKNOWN_OFFSET  0xFFFFFFFF
+
 typedef struct Exynos4210PmuState {
     SysBusDevice busdev;
     MemoryRegion iomem;
     uint32_t     reg[PMU_NUM_OF_REGISTERS];
 } Exynos4210PmuState;
 
-static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
-                                    unsigned size)
+static uint32_t exynos4210_pmu_get_register_index(Exynos4210PmuState *s,
+                                                  uint32_t offset)
 {
-    Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
-    unsigned i;
     const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
+    uint32_t i;
 
     for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
         if (reg_p->offset == offset) {
-            PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,
-                                   (uint32_t)offset, s->reg[i]);
-            return s->reg[i];
+            return i;
         }
         reg_p++;
     }
-    PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset);
-    return 0;
+
+    return PMU_UNKNOWN_OFFSET;
+}
+
+static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
+                                    unsigned size)
+{
+    Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
+    uint32_t index = exynos4210_pmu_get_register_index(s, offset);
+
+    if (index == PMU_UNKNOWN_OFFSET) {
+        PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n",
+                    (uint32_t)offset);
+        return 0;
+    }
+
+    PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n",
+             exynos4210_pmu_regs[index].name, (uint32_t)offset, s->reg[index]);
+
+    return s->reg[index];
 }
 
 static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset,
                                  uint64_t val, unsigned size)
 {
     Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
-    unsigned i;
-    const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
+    uint32_t index = exynos4210_pmu_get_register_index(s, offset);
 
-    for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
-        if (reg_p->offset == offset) {
-            PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
-                    (uint32_t)offset, (uint32_t)val);
-            s->reg[i] = val;
-            return;
-        }
-        reg_p++;
+    if (index == PMU_UNKNOWN_OFFSET) {
+        PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n",
+                                                             (uint32_t)offset);
+        return;
     }
-    PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset);
+
+    PRINT_DEBUG_EXTEND("%s [0x%04x] <- 0x%04x\n",
+             exynos4210_pmu_regs[index].name, (uint32_t)offset, (uint32_t)val);
+
+    s->reg[index] = val;
 }
 
 static const MemoryRegionOps exynos4210_pmu_ops = {
-- 
1.7.5.4