[Qemu-devel] [PATCH 3/3] target-arm: kvm: remove old kernel support.

[Rusty Russell]

This removes old kernel support for cp15 inside struct kvm_regs, and
assumes we have KVM_SET_SREGS support for setting the target.

Signed-off-by: Rusty Russell <address@hidden>

diff --git a/linux-headers/asm-arm/kvm.h b/linux-headers/asm-arm/kvm.h
index 4842e85..8d255f2 100644
--- a/linux-headers/asm-arm/kvm.h
+++ b/linux-headers/asm-arm/kvm.h
@@ -55,15 +55,6 @@ struct kvm_regs {
        __u32 reg15;
        __u32 cpsr;
        __u32 spsr[5];          /* Banked SPSR,  indexed by MODE_  */
-       struct {
-               __u32 c0_midr;
-               __u32 c1_sys;
-               __u32 c2_base0;
-               __u32 c2_base1;
-               __u32 c2_control;
-               __u32 c3_dacr;
-       } cp15;
-
 };
 
 /* Supported Processor Types */
diff --git a/target-arm/kvm.c b/target-arm/kvm.c
index 2c149bd..34741ba 100644
--- a/target-arm/kvm.c
+++ b/target-arm/kvm.c
@@ -39,17 +39,12 @@ int kvm_arch_init_vcpu(CPUARMState *env)
     sregs.target = KVM_ARM_TARGET_CORTEX_A15;
     sregs.num_features = 0;
 
-    /* Ignore failure for compatibility with old kvm versions. */
-    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs) ? 0 : 0;
+    return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 }
 
 #define MSR32_INDEX_OF(coproc, crn, opc1, crm, opc2) \
        (((coproc)<<16) | ((opc1)<<11) | ((crn)<<7) | ((opc2)<<4) | (crm))
 
-/* A modern kernel has a smaller struct kvm_regs, so ioctls differ: */
-#define KVM_GET_REGS_MODERN 2157227649U
-#define KVM_SET_REGS_MODERN 1083485826U
-
 int kvm_arch_put_registers(CPUARMState *env, int level)
 {
     struct kvm_regs regs;
@@ -62,8 +57,6 @@ int kvm_arch_put_registers(CPUARMState *env, int level)
 
     ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
     if (ret < 0)
-       ret = kvm_vcpu_ioctl(env, KVM_GET_REGS_MODERN, &regs);
-    if (ret < 0)
        return ret;
 
     /* We make sure the banked regs are properly set */
@@ -101,9 +94,6 @@ int kvm_arch_put_registers(CPUARMState *env, int level)
     regs.spsr[MODE_ABT] = env->banked_spsr[2];
     regs.spsr[MODE_UND] = env->banked_spsr[3];
 
-    regs.cp15.c0_midr = env->cp15.c0_cpuid;
-    regs.cp15.c1_sys = env->cp15.c1_sys;
-
     cp15.hdr.nmsrs = ARRAY_SIZE(cp15.e);
     cp15.e[0].index = MSR32_INDEX_OF(15, 0, 0, 0, 0); /* MIDR */
     cp15.e[0].data = env->cp15.c0_cpuid;
@@ -111,11 +101,8 @@ int kvm_arch_put_registers(CPUARMState *env, int level)
     cp15.e[1].data = env->cp15.c1_sys;
 
     ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
-    if (ret < 0) {
-       ret = kvm_vcpu_ioctl(env, KVM_SET_REGS_MODERN, &regs);
-       if (ret == 0)
-           ret = kvm_vcpu_ioctl(env, KVM_SET_MSRS, &cp15);
-    }
+    if (ret < 0)
+       ret = kvm_vcpu_ioctl(env, KVM_SET_MSRS, &cp15);
     return ret;
 }
 
@@ -144,6 +131,8 @@ int kvm_arch_get_registers(CPUARMState *env)
     cp15.e[5].index = MSR32_INDEX_OF(15, 3, 0, 0, 0); /* DACR */
 
     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &cp15);
+    if (ret < 0)
+       return ret;
 
     /* First, let's transfer the banked state */
     cpsr_write(env, regs.cpsr, 0xFFFFFFFF);
@@ -181,22 +170,6 @@ int kvm_arch_get_registers(CPUARMState *env)
     env->regs[14] = env->banked_r14[bn];
     env->spsr = env->banked_spsr[bn];
 
-    /* Old KVM version. */
-    if (ret != 0) {
-           //env->cp15.c0_cpuid = regs.cp15.c0_midr;
-           env->cp15.c1_sys = regs.cp15.c1_sys;
-           env->cp15.c2_base0 = regs.cp15.c2_base0;
-           env->cp15.c2_base1 = regs.cp15.c2_base1;
-
-           /* This is ugly, but necessary for GDB compatibility */
-           env->cp15.c2_control = regs.cp15.c2_control;
-           env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> 
regs.cp15.c2_control);
-           env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> 
regs.cp15.c2_control);
-
-           env->cp15.c3 = regs.cp15.c3_dacr;
-           return 0;
-    }
-
     //env->cp15.c0_cpuid = cp15.e[0].data;
     env->cp15.c1_sys = cp15.e[1].data;
     env->cp15.c2_base0 = cp15.e[2].data;