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[Qemu-devel] [RFC 12/19] create struct X86CPUModelTableEntry
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [RFC 12/19] create struct X86CPUModelTableEntry |
Date: |
Thu, 2 Aug 2012 23:59:19 -0300 |
X86CPUDefinition will be reused in other places, so remove the fields
that are specific to the CPU model name table ('name', 'is_builtin', and
'next') and put them into a separate struct.
Signed-off-by: Eduardo Habkost <address@hidden>
---
target-i386/cpu.c | 132 +++++++++++++++++++++++++++++++++++++-----------------
1 file changed, 92 insertions(+), 40 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 4f67ecc..3f6efdb 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -223,8 +223,6 @@ static void add_flagname_to_bitmaps(const char *flagname,
uint32_t *features,
}
typedef struct X86CPUDefinition {
- struct X86CPUDefinition *next;
- const char *name;
uint32_t level;
uint32_t vendor1, vendor2, vendor3;
int family;
@@ -236,7 +234,6 @@ typedef struct X86CPUDefinition {
uint32_t xlevel;
char model_id[48];
int vendor_override;
- bool is_builtin;
/* Store the results of Centaur's CPUID instructions */
uint32_t ext4_features;
uint32_t xlevel2;
@@ -282,15 +279,24 @@ typedef struct X86CPUDefinition {
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
#define TCG_SVM_FEATURES 0
+
+typedef struct X86CPUModelTableEntry {
+ const char *name;
+ struct X86CPUModelTableEntry *next;
+ bool is_builtin;
+ X86CPUDefinition cpudef;
+} X86CPUModelTableEntry;
+
/* maintains list of cpu model definitions
*/
-static X86CPUDefinition *x86_defs = {NULL};
+static X86CPUModelTableEntry *x86_defs = {NULL};
/* built-in cpu model definitions (deprecated)
*/
-static X86CPUDefinition builtin_x86_defs[] = {
+static X86CPUModelTableEntry builtin_x86_defs[] = {
{
- .name = "qemu64",
+ .name = "qemu64",
+ .cpudef = {
.level = 4,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
@@ -307,9 +313,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
.xlevel = 0x8000000A,
+ },
},
{
- .name = "phenom",
+ .name = "phenom",
+ .cpudef = {
.level = 5,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
@@ -335,9 +343,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
.xlevel = 0x8000001A,
.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
+ },
},
{
- .name = "core2duo",
+ .name = "core2duo",
+ .cpudef = {
.level = 10,
.family = 6,
.model = 15,
@@ -353,9 +363,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
+ },
},
{
- .name = "kvm64",
+ .name = "kvm64",
+ .cpudef = {
.level = 5,
.vendor1 = CPUID_VENDOR_INTEL_1,
.vendor2 = CPUID_VENDOR_INTEL_2,
@@ -379,9 +391,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = 0,
.xlevel = 0x80000008,
.model_id = "Common KVM processor"
+ },
},
{
- .name = "qemu32",
+ .name = "qemu32",
+ .cpudef = {
.level = 4,
.family = 6,
.model = 3,
@@ -389,9 +403,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features = PPRO_FEATURES,
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
.xlevel = 0x80000004,
+ },
},
{
- .name = "kvm32",
+ .name = "kvm32",
+ .cpudef = {
.level = 5,
.family = 15,
.model = 6,
@@ -403,9 +419,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = 0,
.xlevel = 0x80000008,
.model_id = "Common 32-bit KVM processor"
+ },
},
{
- .name = "coreduo",
+ .name = "coreduo",
+ .cpudef = {
.level = 10,
.family = 6,
.model = 14,
@@ -418,45 +436,55 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext2_features = CPUID_EXT2_NX,
.xlevel = 0x80000008,
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
+ },
},
{
- .name = "486",
+ .name = "486",
+ .cpudef = {
.level = 1,
.family = 4,
.model = 0,
.stepping = 0,
.features = I486_FEATURES,
.xlevel = 0,
+ },
},
{
- .name = "pentium",
+ .name = "pentium",
+ .cpudef = {
.level = 1,
.family = 5,
.model = 4,
.stepping = 3,
.features = PENTIUM_FEATURES,
.xlevel = 0,
+ },
},
{
- .name = "pentium2",
+ .name = "pentium2",
+ .cpudef = {
.level = 2,
.family = 6,
.model = 5,
.stepping = 2,
.features = PENTIUM2_FEATURES,
.xlevel = 0,
+ },
},
{
- .name = "pentium3",
+ .name = "pentium3",
+ .cpudef = {
.level = 2,
.family = 6,
.model = 7,
.stepping = 3,
.features = PENTIUM3_FEATURES,
.xlevel = 0,
+ },
},
{
- .name = "athlon",
+ .name = "athlon",
+ .cpudef = {
.level = 2,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
@@ -467,9 +495,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
CPUID_MCA,
.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
.xlevel = 0x80000008,
+ },
},
{
- .name = "n270",
+ .name = "n270",
+ .cpudef = {
/* original is on level 10 */
.level = 5,
.family = 6,
@@ -485,9 +515,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000000A,
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
+ },
},
{
- .name = "Conroe",
+ .name = "Conroe",
+ .cpudef = {
.level = 2,
.vendor1 = CPUID_VENDOR_INTEL_1,
.vendor2 = CPUID_VENDOR_INTEL_2,
@@ -505,9 +537,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000000A,
.model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
+ },
},
{
- .name = "Penryn",
+ .name = "Penryn",
+ .cpudef = {
.level = 2,
.vendor1 = CPUID_VENDOR_INTEL_1,
.vendor2 = CPUID_VENDOR_INTEL_2,
@@ -526,9 +560,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000000A,
.model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
+ },
},
{
- .name = "Nehalem",
+ .name = "Nehalem",
+ .cpudef = {
.level = 2,
.vendor1 = CPUID_VENDOR_INTEL_1,
.vendor2 = CPUID_VENDOR_INTEL_2,
@@ -547,9 +583,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000000A,
.model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
+ },
},
{
- .name = "Westmere",
+ .name = "Westmere",
+ .cpudef = {
.level = 11,
.vendor1 = CPUID_VENDOR_INTEL_1,
.vendor2 = CPUID_VENDOR_INTEL_2,
@@ -569,9 +607,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000000A,
.model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
+ },
},
{
- .name = "SandyBridge",
+ .name = "SandyBridge",
+ .cpudef = {
.level = 0xd,
.vendor1 = CPUID_VENDOR_INTEL_1,
.vendor2 = CPUID_VENDOR_INTEL_2,
@@ -594,9 +634,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000000A,
.model_id = "Intel Xeon E312xx (Sandy Bridge)",
+ },
},
{
- .name = "Opteron_G1",
+ .name = "Opteron_G1",
+ .cpudef = {
.level = 5,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
@@ -618,9 +660,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
.xlevel = 0x80000008,
.model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
+ },
},
{
- .name = "Opteron_G2",
+ .name = "Opteron_G2",
+ .cpudef = {
.level = 5,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
@@ -644,9 +688,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
.ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
+ },
},
{
- .name = "Opteron_G3",
+ .name = "Opteron_G3",
+ .cpudef = {
.level = 5,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
@@ -672,9 +718,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
.xlevel = 0x80000008,
.model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
+ },
},
{
- .name = "Opteron_G4",
+ .name = "Opteron_G4",
+ .cpudef = {
.level = 0xd,
.vendor1 = CPUID_VENDOR_AMD_1,
.vendor2 = CPUID_VENDOR_AMD_2,
@@ -704,6 +752,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_LAHF_LM,
.xlevel = 0x8000001A,
.model_id = "AMD Opteron 62xx class CPU",
+ },
},
};
@@ -722,11 +771,11 @@ static int cpu_x86_fill_model_id(char *str)
return 0;
}
+/* Fill X86CPUDefinition struct with host CPU features */
static int cpu_x86_fill_host(X86CPUDefinition *x86_cpu_def)
{
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
- x86_cpu_def->name = "host";
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
x86_cpu_def->level = eax;
x86_cpu_def->vendor1 = ebx;
@@ -1234,7 +1283,7 @@ error:
static int cpu_x86_find_by_name(X86CPUDefinition *x86_cpu_def, const char
*name)
{
- X86CPUDefinition *def;
+ X86CPUModelTableEntry *def;
for (def = x86_defs; def; def = def->next) {
if (name && !strcmp(name, def->name)) {
@@ -1247,7 +1296,7 @@ static int cpu_x86_find_by_name(X86CPUDefinition
*x86_cpu_def, const char *name)
} else if (!def) {
goto error;
} else {
- memcpy(x86_cpu_def, def, sizeof(*def));
+ memcpy(x86_cpu_def, &def->cpudef, sizeof(*def));
}
return 0;
error:
@@ -1324,7 +1373,7 @@ void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf,
const char *optarg)
unsigned char model = !strcmp("?model", optarg);
unsigned char dump = !strcmp("?dump", optarg);
unsigned char cpuid = !strcmp("?cpuid", optarg);
- X86CPUDefinition *def;
+ X86CPUModelTableEntry *deft;
char buf[256];
if (cpuid) {
@@ -1339,8 +1388,10 @@ void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf,
const char *optarg)
(*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
return;
}
- for (def = x86_defs; def; def = def->next) {
- snprintf(buf, sizeof(buf), def->is_builtin ? "[%s]" : "%s", def->name);
+ for (deft = x86_defs; deft; deft = deft->next) {
+ X86CPUDefinition *def = &deft->cpudef;
+ snprintf(buf, sizeof(buf), deft->is_builtin ? "[%s]" : "%s",
+ deft->name);
if (model || dump) {
(*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
} else {
@@ -1505,12 +1556,13 @@ static void setfeatures(uint32_t *pval, const char *str,
*/
static int cpudef_setfield(const char *name, const char *str, void *opaque)
{
- X86CPUDefinition *def = opaque;
+ X86CPUModelTableEntry *deft = opaque;
+ X86CPUDefinition *def = &deft->cpudef;
int err = 0;
if (!strcmp(name, "name")) {
- g_free((void *)def->name);
- def->name = g_strdup(str);
+ g_free((void *)deft->name);
+ deft->name = g_strdup(str);
} else if (!strcmp(name, "model_id")) {
strncpy(def->model_id, str, sizeof(def->model_id));
} else if (!strcmp(name, "level")) {
@@ -1550,7 +1602,7 @@ static int cpudef_setfield(const char *name, const char
*str, void *opaque)
*/
static int cpudef_register(QemuOpts *opts, void *opaque)
{
- X86CPUDefinition *def = g_malloc0(sizeof(X86CPUDefinition));
+ X86CPUModelTableEntry *def = g_malloc0(sizeof(X86CPUModelTableEntry));
qemu_opt_foreach(opts, cpudef_setfield, def, 1);
def->next = x86_defs;
@@ -1574,7 +1626,7 @@ void x86_cpudef_setup(void)
static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon"
};
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
- X86CPUDefinition *def = &builtin_x86_defs[i];
+ X86CPUModelTableEntry *def = &builtin_x86_defs[i];
def->next = x86_defs;
def->is_builtin = true;
@@ -1582,9 +1634,9 @@ void x86_cpudef_setup(void)
/* have the QEMU version in .model_id */
for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
if (strcmp(model_with_versions[j], def->name) == 0) {
- pstrcpy(def->model_id, sizeof(def->model_id),
+ pstrcpy(def->cpudef.model_id, sizeof(def->cpudef.model_id),
"QEMU Virtual CPU version ");
- pstrcat(def->model_id, sizeof(def->model_id),
+ pstrcat(def->cpudef.model_id, sizeof(def->cpudef.model_id),
qemu_get_version());
break;
}
--
1.7.11.2
- [Qemu-devel] [RFC 05/19] cpu_x86_build_from_name: use strtok_r(), (continued)
- [Qemu-devel] [RFC 05/19] cpu_x86_build_from_name: use strtok_r(), Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 13/19] move X86CPUDefinition to cpu-qom.h, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 01/19] target-i386/cpu.c: coding style fixes, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 18/19] register a class for each CPU model, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 08/19] i386: extract CPU model lookup to a separate function, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 07/19] i386: cpu: extract parsing of feature strings to separate function, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 10/19] move CPU object creation to cpu.c, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 03/19] i386: x86_def_t: rename 'flags' field, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 11/19] rename x86_def_t to X86CPUDefinition, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 06/19] i386: cpu: extract the full feature list before parsing it, Eduardo Habkost, 2012/08/02
- [Qemu-devel] [RFC 12/19] create struct X86CPUModelTableEntry,
Eduardo Habkost <=
- [Qemu-devel] [RFC 04/19] rename cpu_x86_find_by_name to x86_cpu_build_from_name, Eduardo Habkost, 2012/08/02