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[Qemu-devel] [PATCH 08/19] unicore32-softmmu: Add puv3 interrupt support
From: |
gxt |
Subject: |
[Qemu-devel] [PATCH 08/19] unicore32-softmmu: Add puv3 interrupt support |
Date: |
Tue, 7 Aug 2012 18:00:48 +0800 |
From: Guan Xuetao <address@hidden>
This patch adds puv3 interrupt support, include interrupt controler
device simulation and interrupt handler in puv3 machine.
Signed-off-by: Guan Xuetao <address@hidden>
---
hw/Makefile.objs | 3 +
hw/puv3.c | 23 +++++++++-
hw/puv3_intc.c | 135 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 160 insertions(+), 1 deletions(-)
create mode 100644 hw/puv3_intc.c
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 8327e55..50554b6 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -66,6 +66,9 @@ hw-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
hw-obj-$(CONFIG_XILINX_AXI) += xilinx_axienet.o
+# PKUnity SoC devices
+hw-obj-$(CONFIG_PUV3) += puv3_intc.o
+
# PCI watchdog devices
hw-obj-$(CONFIG_PCI) += wdt_i6300esb.o
diff --git a/hw/puv3.c b/hw/puv3.c
index 0dc129d..2870455 100644
--- a/hw/puv3.c
+++ b/hw/puv3.c
@@ -22,9 +22,30 @@
#define KERNEL_LOAD_ADDR 0x03000000
#define KERNEL_MAX_SIZE 0x00800000 /* Just a guess */
+static void puv3_intc_cpu_handler(void *opaque, int irq, int level)
+{
+ CPUUniCore32State *env = opaque;
+
+ assert(irq == 0);
+ if (level) {
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+}
+
static void puv3_soc_init(CPUUniCore32State *env)
{
- /* TODO */
+ qemu_irq *cpu_intc, irqs[PUV3_IRQS_NR];
+ DeviceState *dev;
+ int i;
+
+ /* Initialize interrupt controller */
+ cpu_intc = qemu_allocate_irqs(puv3_intc_cpu_handler, env, 1);
+ dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, *cpu_intc);
+ for (i = 0; i < PUV3_IRQS_NR; i++) {
+ irqs[i] = qdev_get_gpio_in(dev, i);
+ }
}
static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size)
diff --git a/hw/puv3_intc.c b/hw/puv3_intc.c
new file mode 100644
index 0000000..9e0b975
--- /dev/null
+++ b/hw/puv3_intc.c
@@ -0,0 +1,135 @@
+/*
+ * INTC device simulation in PKUnity SoC
+ *
+ * Copyright (C) 2010-2012 Guan Xuetao
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, or any later version.
+ * See the COPYING file in the top-level directory.
+ */
+#include "sysbus.h"
+
+#undef DEBUG_PUV3
+#include "puv3.h"
+
+typedef struct {
+ SysBusDevice busdev;
+ MemoryRegion iomem;
+ qemu_irq parent_irq;
+
+ uint32_t reg_ICMR;
+ uint32_t reg_ICPR;
+} PUV3INTCState;
+
+/* Update interrupt status after enabled or pending bits have been changed. */
+static void puv3_intc_update(PUV3INTCState *s)
+{
+ if (s->reg_ICMR & s->reg_ICPR) {
+ qemu_irq_raise(s->parent_irq);
+ } else {
+ qemu_irq_lower(s->parent_irq);
+ }
+}
+
+/* Process a change in an external INTC input. */
+static void puv3_intc_handler(void *opaque, int irq, int level)
+{
+ PUV3INTCState *s = opaque;
+
+ DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
+ if (level) {
+ s->reg_ICPR |= (1 << irq);
+ } else {
+ s->reg_ICPR &= ~(1 << irq);
+ }
+ puv3_intc_update(s);
+}
+
+static uint64_t puv3_intc_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
+{
+ PUV3INTCState *s = opaque;
+ uint32_t ret = 0;
+
+ switch (offset) {
+ case 0x04: /* INTC_ICMR */
+ ret = s->reg_ICMR;
+ break;
+ case 0x0c: /* INTC_ICIP */
+ ret = s->reg_ICPR; /* the same value with ICPR */
+ break;
+ default:
+ DPRINTF("Bad offset %x\n", (int)offset);
+ }
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
+ return ret;
+}
+
+static void puv3_intc_write(void *opaque, target_phys_addr_t offset,
+ uint64_t value, unsigned size)
+{
+ PUV3INTCState *s = opaque;
+
+ DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
+ switch (offset) {
+ case 0x00: /* INTC_ICLR */
+ case 0x14: /* INTC_ICCR */
+ break;
+ case 0x04: /* INTC_ICMR */
+ s->reg_ICMR = value;
+ break;
+ default:
+ DPRINTF("Bad offset 0x%x\n", (int)offset);
+ return;
+ }
+ puv3_intc_update(s);
+}
+
+static const MemoryRegionOps puv3_intc_ops = {
+ .read = puv3_intc_read,
+ .write = puv3_intc_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static int puv3_intc_init(SysBusDevice *dev)
+{
+ PUV3INTCState *s = FROM_SYSBUS(PUV3INTCState, dev);
+
+ qdev_init_gpio_in(&s->busdev.qdev, puv3_intc_handler, PUV3_IRQS_NR);
+ sysbus_init_irq(&s->busdev, &s->parent_irq);
+
+ s->reg_ICMR = 0;
+ s->reg_ICPR = 0;
+
+ memory_region_init_io(&s->iomem, &puv3_intc_ops, s, "puv3_intc",
+ PUV3_REGS_OFFSET);
+ sysbus_init_mmio(dev, &s->iomem);
+
+ return 0;
+}
+
+static void puv3_intc_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = puv3_intc_init;
+}
+
+static const TypeInfo puv3_intc_info = {
+ .name = "puv3_intc",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(PUV3INTCState),
+ .class_init = puv3_intc_class_init,
+};
+
+static void puv3_intc_register_type(void)
+{
+ type_register_static(&puv3_intc_info);
+}
+
+type_init(puv3_intc_register_type)
--
1.7.0.4
- [Qemu-devel] [PATCH 02/19] unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support, (continued)
- [Qemu-devel] [PATCH 02/19] unicore32-softmmu: Add coprocessor 0(sysctrl) and 1(ocd) instruction support, gxt, 2012/08/07
- [Qemu-devel] [PATCH 03/19] unicore32-softmmu: Make UniCore32 cpuid & exceptions correct and runable, gxt, 2012/08/07
- [Qemu-devel] [PATCH 04/19] target-unicore32: Drop UC32_CPUID macros, gxt, 2012/08/07
- [Qemu-devel] [PATCH 12/19] unicore32-softmmu: Add puv3 dma support, gxt, 2012/08/07
- [Qemu-devel] [PATCH 06/19] unicore32-softmmu: Make sure that kernel can access user space, gxt, 2012/08/07
- [Qemu-devel] [PATCH 07/19] unicore32-softmmu: Add puv3 soc/board support, gxt, 2012/08/07
- [Qemu-devel] [PATCH 11/19] unicore32-softmmu: Add puv3 pm support, gxt, 2012/08/07
- [Qemu-devel] [PATCH 13/19] unicore32-softmmu: Add ps2 support, gxt, 2012/08/07
- [Qemu-devel] [PATCH 05/19] unicore32-softmmu: Implement softmmu specific functions, gxt, 2012/08/07
- [Qemu-devel] [PATCH 10/19] unicore32-softmmu: Add puv3 gpio support, gxt, 2012/08/07
- [Qemu-devel] [PATCH 08/19] unicore32-softmmu: Add puv3 interrupt support,
gxt <=
- [Qemu-devel] [PATCH 17/19] unicore32: Disintegrate cpu_dump_state_ucf64 function, gxt, 2012/08/07
- [Qemu-devel] [PATCH 19/19] unicore32-softmmu: Add a minimal curses screen support, gxt, 2012/08/07
- [Qemu-devel] [PATCH 18/19] unicore32: Close dump-option of cpu_dump_state_ucf64 function, gxt, 2012/08/07
- [Qemu-devel] [PATCH 16/19] unicore32: Split UniCore-F64 instruction helpers from helper.c, gxt, 2012/08/07
- [Qemu-devel] [PATCH 15/19] unicore32-softmmu: Add is_default setting for puv3 machine, gxt, 2012/08/07
- [Qemu-devel] [PATCH 14/19] unicore32-softmmu: Add maintainer information for UniCore32 machine, gxt, 2012/08/07
- [Qemu-devel] [PATCH 09/19] unicore32-softmmu: Add puv3 ostimer support, gxt, 2012/08/07
- Re: [Qemu-devel] [PATCH 00/19] unicore32: Add unicore32-softmmu support, Blue Swirl, 2012/08/09