Re: [Qemu-devel] [PATCH v4 5/5] i8259: fix dynamically masking slave IRQs with IMR register

[Jan Kiszka]

On 2012-09-03 11:34, Paolo Bonzini wrote:
> Il 03/09/2012 10:51, Jan Kiszka ha scritto:
>> The only thing that worries me is that we just consider the PC so far
>> while the i8259 is also used on different architectures (PPC, MIPS, Alpha?).
> 
> Why is this a problem?  All of them use IRQ2 for a cascade, and initialize
> icw3 to 0x4/0x2 (I checked OpenBIOS, rth's palcode for Alpha, and Linux).

IRQ2 is already hard-coded in QEMU (we had to patch this for our machine
emulation, but less in recent versions), that is not the point. I'm
concerned about the behavioral changes we are discussing here, ie. the
special handling of cascading interrupt inputs.

> 
> BTW, from the palcode it looks like Alpha wants LTIM=1, so it would be nice
> to implement that one as well:
> 
>   /* ??? MILO initializes the PIC as edge triggered; I do not know how SRM
>      initializes them.  However, Linux seems to expect that these are level
>      triggered.  That may be a kernel bug, but level triggers are more
>      reliable anyway so lets go with that.  */
> 
>   /* Initialize level triggers.  The CY82C693UB that's on real alpha
>      hardware doesn't have this; this is a PIIX extension.  However,
>      QEMU doesn't implement regular level triggers.  */
>   outb(0xff, PORT_PIC2_ELCR);
>   outb(0xff, PORT_PIC1_ELCR);

Just takes someone to write the patch, as usual. :)

Jan

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