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[Qemu-devel] [PATCH 004/126] target-s390: Fix disassembly of cpsdr
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 004/126] target-s390: Fix disassembly of cpsdr |
Date: |
Sun, 9 Sep 2012 14:04:22 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
s390-dis.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/s390-dis.c b/s390-dis.c
index bbdd239..3759164 100644
--- a/s390-dis.c
+++ b/s390-dis.c
@@ -673,7 +673,9 @@ static const struct s390_operand s390_operands[] =
This is just a workaround for existing code e.g. glibc. */
#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */
#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */
-#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */
+/* QEMU-MOD */
+#define INSTR_RRF_F0FF2 4, { F_24,F_28,F_16,0,0,0 } /* e.g. cpsdr */
+/* QEMU-END */
#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */
#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */
#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */
--
1.7.11.4
- [Qemu-devel] [PATCH 000/126] Rewrite s390x translator, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 001/126] tcg: Add TCGV_IS_UNUSED_*, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 006/126] target-s390: Add missing temp_free in gen_op_calc_cc, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 002/126] tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYS, Richard Henderson, 2012/09/09
- [Qemu-devel] [PATCH 004/126] target-s390: Fix disassembly of cpsdr,
Richard Henderson <=
- [Qemu-devel] [PATCH 005/126] target-s390: Fix gdbstub, Richard Henderson, 2012/09/09
[Qemu-devel] [PATCH 003/126] target-s390: Disassemble more z10 and z196 opcodes, Richard Henderson, 2012/09/09
[Qemu-devel] [PATCH 007/126] target-s390: Use TCG registers for FPR, Richard Henderson, 2012/09/09