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[Qemu-devel] [PATCH v3 04/10] target-xtensa: specialize softfloat NaN ru
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH v3 04/10] target-xtensa: specialize softfloat NaN rules |
Date: |
Wed, 19 Sep 2012 04:23:53 +0400 |
NaN propagation rule: leftmost NaN in the expression gets propagated to
the result.
Signed-off-by: Max Filippov <address@hidden>
---
fpu/softfloat-specialize.h | 5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
index 50b54b8..a1d489e 100644
--- a/fpu/softfloat-specialize.h
+++ b/fpu/softfloat-specialize.h
@@ -64,7 +64,8 @@ const float16 float16_default_nan = const_float16(0xFE00);
*----------------------------------------------------------------------------*/
#if defined(TARGET_SPARC)
const float32 float32_default_nan = const_float32(0x7FFFFFFF);
-#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
+#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
+ defined(TARGET_XTENSA)
const float32 float32_default_nan = const_float32(0x7FC00000);
#elif SNAN_BIT_IS_ONE
const float32 float32_default_nan = const_float32(0x7FBFFFFF);
@@ -403,7 +404,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag
bIsQNaN, flag bIsSNaN,
return 1;
}
}
-#elif defined(TARGET_PPC)
+#elif defined(TARGET_PPC) || defined(TARGET_XTENSA)
static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag aIsLargerSignificand)
{
--
1.7.7.6
- [Qemu-devel] [PATCH v3 00/10] target-xtensa: implement FP coprocessor option, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 01/10] softfloat: make float_muladd_negate_* flags independent, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 02/10] softfloat: add NO_SIGNALING_NANS, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 03/10] target-xtensa: handle boolean option in overlays, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 04/10] target-xtensa: specialize softfloat NaN rules,
Max Filippov <=
- [Qemu-devel] [PATCH v3 05/10] target-xtensa: add FP registers, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 06/10] target-xtensa: implement LSCX and LSCI groups, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 07/10] target-xtensa: implement FP0 arithmetic, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 08/10] target-xtensa: implement FP0 conversions, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 09/10] target-xtensa: implement FP1 group, Max Filippov, 2012/09/18
- [Qemu-devel] [PATCH v3 10/10] target-xtensa: implement coprocessor context option, Max Filippov, 2012/09/18
- Re: [Qemu-devel] [PATCH v3 00/10] target-xtensa: implement FP coprocessor option, Blue Swirl, 2012/09/22