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[Qemu-devel] [PATCH 1/2] tcg: Streamline movcond_i64 using 32-bit arithm
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 1/2] tcg: Streamline movcond_i64 using 32-bit arithmetic |
Date: |
Mon, 24 Sep 2012 13:44:59 -0700 |
Avoiding 64-bit arithmetic (outside of the compare) reduces the
generated op count from 15 to 12, and the generated code size on
i686 from 105 to 88 bytes.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/tcg-op.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 6d28f82..c32646e 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2141,6 +2141,25 @@ static inline void tcg_gen_movcond_i64(TCGCond cond,
TCGv_i64 ret,
TCGv_i64 c1, TCGv_i64 c2,
TCGv_i64 v1, TCGv_i64 v2)
{
+#if TCG_TARGET_REG_BITS == 32
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
+ TCGV_LOW(c1), TCGV_HIGH(c1),
+ TCGV_LOW(c2), TCGV_HIGH(c2), cond);
+ tcg_gen_neg_i32(t0, t0);
+
+ tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
+ tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
+ tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
+
+ tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
+ tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
+ tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
+
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+#else
if (TCG_TARGET_HAS_movcond_i64) {
tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
} else {
@@ -2154,6 +2173,7 @@ static inline void tcg_gen_movcond_i64(TCGCond cond,
TCGv_i64 ret,
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
}
+#endif
}
/***************************************/
--
1.7.11.4