Re: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI controller

[Avi Kivity]

On 10/04/2012 06:50 PM, Alexander Graf wrote:
>>> 
>>> No, it also meets (2). The PCI address space is identical to the CPU memory
>>> space in our mapping right now. So if the guest maps BAR0 somewhere, it
>>> automatically maps CCSR into CPU address space, which exposes it to PCI 
>>> address
>>> space.
>> 
>> Really? I think on powerpc the pci address space is defined as: it maps the 
>> outbound window just below 0x1_0000_0000, then CCSR and then inbound window. 
>> So inbound window is 1:1 map if guest physical starts from 0x0. But I do not 
>> think CCSR is 1:1 map in pci address space and cpu address space. 
> 
> In QEMU, we map everything 1:1 today.

An unmerged patch set entitled "Integrate DMA into the memory API"
changes that.  I'll be happy to work with you to make use of it to
emulate the hardware properly, it will give me a nice test case.

-- 
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