[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 10/14] target-mips: implement movn/movz using movcon
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 10/14] target-mips: implement movn/movz using movcond |
Date: |
Tue, 9 Oct 2012 22:27:34 +0200 |
Avoid the branches in movn/movz implementation and replace them with
movcond. Also update a wrong command.
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-mips/translate.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b6eb46a..9a22432 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1920,35 +1920,32 @@ static void gen_cond_move(CPUMIPSState *env,
DisasContext *ctx, uint32_t opc,
int rd, int rs, int rt)
{
const char *opn = "cond move";
- int l1;
+ TCGv t0, t1, t2;
if (rd == 0) {
- /* If no destination, treat it as a NOP.
- For add & sub, we must generate the overflow exception when needed.
*/
+ /* If no destination, treat it as a NOP. */
MIPS_DEBUG("NOP");
return;
}
- l1 = gen_new_label();
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, rt);
+ t1 = tcg_const_tl(0);
+ t2 = tcg_temp_new();
+ gen_load_gpr(t2, rs);
switch (opc) {
case OPC_MOVN:
- if (likely(rt != 0))
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1);
- else
- tcg_gen_br(l1);
+ tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
opn = "movn";
break;
case OPC_MOVZ:
- if (likely(rt != 0))
- tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1);
+ tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]);
opn = "movz";
break;
}
- if (rs != 0)
- tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]);
- else
- tcg_gen_movi_tl(cpu_gpr[rd], 0);
- gen_set_label(l1);
+ tcg_temp_free(t2);
+ tcg_temp_free(t1);
+ tcg_temp_free(t0);
(void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]);
--
1.7.10.4
- [Qemu-devel] [PATCH 13/14] target-mips: fix TLBR wrt SEGMask, (continued)
- [Qemu-devel] [PATCH 13/14] target-mips: fix TLBR wrt SEGMask, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 04/14] target-mips: use softfloat constants when possible, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 05/14] target-mips: cleanup load/store operations, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 11/14] target-mips: optimize ddiv/ddivu/div/divu with movcond, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 06/14] target-mips: optimize load operations, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 02/14] target-mips: use the softfloat floatXX_muladd functions, Aurelien Jarno, 2012/10/09
- [Qemu-devel] [PATCH 10/14] target-mips: implement movn/movz using movcond,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 08/14] target-mips: implement unaligned loads using TCG, Aurelien Jarno, 2012/10/09