[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr |
Date: |
Tue, 9 Oct 2012 15:04:08 -0700 |
Infrastructure to be used to clean up handling of temporaries.
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 6cef96b..eec0db0 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -83,7 +83,9 @@ typedef struct DisasContext {
struct TranslationBlock *tb;
sparc_def_t *def;
TCGv_i32 t32[3];
+ TCGv ttl[5];
int n_t32;
+ int n_ttl;
} DisasContext;
typedef struct {
@@ -263,6 +265,49 @@ static inline void gen_address_mask(DisasContext *dc, TCGv
addr)
#endif
}
+static inline TCGv get_temp_tl(DisasContext *dc)
+{
+ TCGv t;
+ assert(dc->n_ttl < ARRAY_SIZE(dc->ttl));
+ dc->ttl[dc->n_ttl++] = t = tcg_temp_new();
+ return t;
+}
+
+static inline TCGv gen_load_gpr(DisasContext *dc, int reg)
+{
+ if (reg == 0 || reg >= 8) {
+ TCGv t = get_temp_tl(dc);
+ if (reg == 0) {
+ tcg_gen_movi_tl(t, 0);
+ } else {
+ tcg_gen_ld_tl(t, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
+ }
+ return t;
+ } else {
+ return cpu_gregs[reg];
+ }
+}
+
+static inline void gen_store_gpr(DisasContext *dc, int reg, TCGv v)
+{
+ if (reg > 0) {
+ if (reg < 8) {
+ tcg_gen_mov_tl(cpu_gregs[reg], v);
+ } else {
+ tcg_gen_st_tl(v, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
+ }
+ }
+}
+
+static inline TCGv gen_dest_gpr(DisasContext *dc, int reg)
+{
+ if (reg == 0 || reg >= 8) {
+ return get_temp_tl(dc);
+ } else {
+ return cpu_gregs[reg];
+ }
+}
+
static inline void gen_movl_reg_TN(int reg, TCGv tn)
{
if (reg == 0)
@@ -5229,6 +5274,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
}
dc->n_t32 = 0;
}
+ if (dc->n_ttl != 0) {
+ int i;
+ for (i = dc->n_ttl - 1; i >= 0; --i) {
+ tcg_temp_free(dc->ttl[i]);
+ }
+ dc->n_ttl = 0;
+ }
}
static inline void gen_intermediate_code_internal(TranslationBlock * tb,
--
1.7.11.4
- [Qemu-devel] [PATCH 00/20] target-sparc: Cleanup handling of temps, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 01/20] target-sparc: Add gen_load/store/dest_gpr,
Richard Henderson <=
- [Qemu-devel] [PATCH 04/20] target-sparc: Convert asi helpers to gen_*_gpr, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 05/20] target-sparc: Convert swap to gen_load/store_gpr, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 07/20] target-sparc: Cleanup cpu_src[12] allocation, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 02/20] target-sparc: Conversion to gen_*_gpr, part 1, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 03/20] target-sparc: Use gen_load_gpr in get_src[12], Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 06/20] target-sparc: Finish conversion to gen_load_gpr, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 09/20] target-sparc: Split out get_temp_i32, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 12/20] target-sparc: Avoid cpu_tmp32 in Write Priv Register, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 10/20] target-sparc: Use get_temp_i32 in gen_dest_fpr_F, Richard Henderson, 2012/10/09
- [Qemu-devel] [PATCH 11/20] target-sparc: Avoid cpu_tmp32 in Read Priv Register, Richard Henderson, 2012/10/09