Re: [Qemu-devel] [RFC v2 4/6] hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC

[Andreas Färber]

Am 10.10.2012 17:07, schrieb Peter Maydell:
> Implement support for using the KVM in-kernel GIC for ARM.
> 
> Signed-off-by: Peter Maydell <address@hidden>
> ---
>  hw/a15mpcore.c       |    8 ++-
>  hw/arm/Makefile.objs |    1 +
>  hw/kvm/arm_gic.c     |  162 
> ++++++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 170 insertions(+), 1 deletion(-)
>  create mode 100644 hw/kvm/arm_gic.c
> 
> diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c
> index fc0a02a..a37fc61 100644
> --- a/hw/a15mpcore.c
> +++ b/hw/a15mpcore.c
> @@ -19,6 +19,7 @@
>   */
>  
>  #include "sysbus.h"
> +#include "kvm.h"
>  
>  /* A15MP private memory region.  */
>  
> @@ -41,7 +42,12 @@ static int a15mp_priv_init(SysBusDevice *dev)
>      A15MPPrivState *s = FROM_SYSBUS(A15MPPrivState, dev);
>      SysBusDevice *busdev;
>  
> -    s->gic = qdev_create(NULL, "arm_gic");
> +    if (kvm_irqchip_in_kernel()) {
> +        s->gic = qdev_create(NULL, "kvm-arm_gic");
> +    } else {
> +        s->gic = qdev_create(NULL, "arm_gic");
> +    }

You could follow x86 more closely by just selecting apic_type. (Then if
we drop/change qdev_create() at some point it's one change less.)

> +
>      qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu);
>      qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq);
>      qdev_prop_set_uint32(s->gic, "revision", 2);
[...]
> diff --git a/hw/kvm/arm_gic.c b/hw/kvm/arm_gic.c
> new file mode 100644
> index 0000000..3ec538d
> --- /dev/null
> +++ b/hw/kvm/arm_gic.c
> @@ -0,0 +1,162 @@
> +/*
> + * ARM Generic Interrupt Controller using KVM in-kernel support
> + *
> + * Copyright (c) 2012 Linaro Limited
> + * Written by Peter Maydell
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "hw/sysbus.h"
> +#include "kvm.h"
> +#include "hw/arm_gic_internal.h"
> +
> +#define TYPE_KVM_ARM_GIC "kvm-arm_gic"

"kvm-arm-gic"?

> +#define KVM_ARM_GIC(obj) \
> +     OBJECT_CHECK(gic_state, (obj), TYPE_KVM_ARM_GIC)
> +#define KVM_ARM_GIC_CLASS(klass) \
> +     OBJECT_CLASS_CHECK(KVMARMGICClass, (klass), TYPE_KVM_ARM_GIC)
> +#define KVM_ARM_GIC_GET_CLASS(obj) \
> +     OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
> +
> +typedef struct KVMARMGICClass {
> +    ARMGICCommonClass parent_class;
> +    int (*parent_init)(SysBusDevice *dev);
> +    void (*parent_reset)(DeviceState *dev);
> +} KVMARMGICClass;
> +
> +static void kvm_arm_gic_set_irq(void *opaque, int irq, int level)
> +{
> +    /* Meaning of the 'irq' parameter:
> +     *  [0..N-1] : external interrupts
> +     *  [N..N+31] : PPI (internal) interrupts for CPU 0
> +     *  [N+32..N+63] : PPI (internal interrupts for CPU 1
> +     *  ...
> +     * Convert this to the kernel's desired encoding, which
> +     * has separate fields in the irq number for type,
> +     * CPU number and interrupt number.
> +     */
> +    gic_state *s = (gic_state *)opaque;

You don't happen to have time to clean up gic_state -> GICState before
spreading its use? ;)

[...]
> +static TypeInfo arm_gic_info = {

static const

> +    .name = TYPE_KVM_ARM_GIC,
> +    .parent = TYPE_ARM_GIC_COMMON,
> +    .instance_size = sizeof(gic_state),
> +    .class_init = kvm_arm_gic_class_init,
> +    .class_size = sizeof(KVMARMGICClass),
> +};
> +
> +static void arm_gic_register_types(void)

kvm_arm_gic_register_types?

> +{
> +    type_register_static(&arm_gic_info);
> +}
> +
> +type_init(arm_gic_register_types)
> 

Andreas

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg