Re: [Qemu-devel] [PATCH 1/2] hw/armv7m_nvic: Implement byte read/write for NVIC SCB_SHPRx registers

[Peter Maydell]

On 12 October 2012 06:43, Andre Beckus <address@hidden> wrote:
> Yes, I was being lazy.  Now that I think about it, we could handle all
> sizes with one block of code directly in the nvic_sysreg_read and
> nvic_sysreg_write functions - the write would look like this:
>
>     for(i = 0; i < size; i++) {
>         s->gic.priority1[(offset - 0xd14) + i][0] =
>             (value >> (i * 8)) & 0xff;
>     }
>
> Then the writeb and readb functions would not be necessary and the SHPR
> code could be removed from the writel and readl functions.  What do you
> think?  Or is the goal to keep each access size isolated to its own
> function?

That sounds like a good idea; we already handle the ID registers in
these functions because they're multi-width accessible.

-- PMM