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[Qemu-devel] [PATCH 2/2] target-sparc: fix FMOVr instruction
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH 2/2] target-sparc: fix FMOVr instruction |
Date: |
Wed, 17 Oct 2012 01:28:35 +0200 |
Like the MOVr instruction, the FMOVr instruction has the condition
encoded between bits 10 and 12.
Cc: Blue Swirl <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-sparc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 6cef96b..6d05e7d 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3154,7 +3154,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
#define FMOVR(sz) \
do { \
DisasCompare cmp; \
- cond = GET_FIELD_SP(insn, 14, 17); \
+ cond = GET_FIELD_SP(insn, 10, 12); \
cpu_src1 = get_src1(insn, cpu_src1); \
gen_compare_reg(&cmp, cond, cpu_src1); \
gen_fmov##sz(dc, &cmp, rd, rs2); \
--
1.7.10.4