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Re: [Qemu-devel] [PATCH v11 06/14] target-mips: Add ASE DSP arithmetic i
From: |
Jia Liu |
Subject: |
Re: [Qemu-devel] [PATCH v11 06/14] target-mips: Add ASE DSP arithmetic instructions |
Date: |
Wed, 17 Oct 2012 12:05:27 +0800 |
Hi Aurelien,
On Wed, Oct 17, 2012 at 7:23 AM, Aurelien Jarno <address@hidden> wrote:
> On Tue, Oct 16, 2012 at 12:39:10AM +0800, Jia Liu wrote:
>> Add MIPS ASE DSP Arithmetic instructions.
>>
>> Signed-off-by: Jia Liu <address@hidden>
>> ---
>> target-mips/dsp_helper.c | 892
>> ++++++++++++++++++++++++++++++++++++++++++++++
>> target-mips/helper.h | 126 +++++++
>> target-mips/translate.c | 848 ++++++++++++++++++++++++++++++++++++++++++-
>> 3 files changed, 1863 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
>> index 1c656a0..99fc8a3 100644
>> --- a/target-mips/dsp_helper.c
>> +++ b/target-mips/dsp_helper.c
>> @@ -1084,3 +1084,895 @@ static inline int32_t mipsdsp_cmp_lt(uint32_t a,
>> uint32_t b)
>> return a < b;
>> }
>> /*** MIPS DSP internal functions end ***/
>> +
>> +#define MIPSDSP_LHI 0xFFFFFFFF00000000ull
>> +#define MIPSDSP_LLO 0x00000000FFFFFFFFull
>> +#define MIPSDSP_HI 0xFFFF0000
>> +#define MIPSDSP_LO 0x0000FFFF
>> +#define MIPSDSP_Q3 0xFF000000
>> +#define MIPSDSP_Q2 0x00FF0000
>> +#define MIPSDSP_Q1 0x0000FF00
>> +#define MIPSDSP_Q0 0x000000FF
>> +
>> +#define MIPSDSP_SPLIT32_8(num, a, b, c, d) \
>> + do { \
>> + a = (num >> 24) & MIPSDSP_Q0; \
>> + b = (num >> 16) & MIPSDSP_Q0; \
>> + c = (num >> 8) & MIPSDSP_Q0; \
>> + d = num & MIPSDSP_Q0; \
>> + } while (0)
>> +
>> +#define MIPSDSP_SPLIT32_16(num, a, b) \
>> + do { \
>> + a = (num >> 16) & MIPSDSP_LO; \
>> + b = num & MIPSDSP_LO; \
>> + } while (0)
>> +
>> +#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a)
>> +#define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \
>> + (((uint32_t)a << 24) | \
>> + (((uint32_t)b << 16) | \
>> + (((uint32_t)c << 8) | \
>> + ((uint32_t)d & 0xFF)))))
>> +#define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \
>> + (((uint32_t)a << 16) | \
>> + ((uint32_t)b & 0xFFFF)))
>> +
>> +#ifdef TARGET_MIPS64
>> +#define MIPSDSP_SPLIT64_16(num, a, b, c, d) \
>> + do { \
>> + a = (num >> 48) & MIPSDSP_LO; \
>> + b = (num >> 32) & MIPSDSP_LO; \
>> + c = (num >> 16) & MIPSDSP_LO; \
>> + d = num & MIPSDSP_LO; \
>> + } while (0)
>> +
>> +#define MIPSDSP_SPLIT64_32(num, a, b) \
>> + do { \
>> + a = (num >> 32) & MIPSDSP_LLO; \
>> + b = num & MIPSDSP_LLO; \
>> + } while (0)
>> +
>> +#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
>> + ((uint64_t)b << 32) | \
>> + ((uint64_t)c << 16) | \
>> + (uint64_t)d)
>> +#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b)
>> +#endif
>> +
>> +/** DSP Arithmetic Sub-class insns **/
>> +#define ARITH_PH(name, func) \
>> +target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \
>> +{ \
>> + uint16_t rsh, rsl, rth, rtl, temph, templ; \
>> + \
>> + MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
>> + MIPSDSP_SPLIT32_16(rt, rth, rtl); \
>> + \
>> + temph = mipsdsp_##func(rsh, rth); \
>> + templ = mipsdsp_##func(rsl, rtl); \
>> + \
>> + return MIPSDSP_RETURN32_16(temph, templ); \
>> +}
>> +
>> +#define ARITH_PH_ENV(name, func) \
>> +target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \
>> + CPUMIPSState *env) \
>> +{ \
>> + uint16_t rsh, rsl, rth, rtl, temph, templ; \
>> + \
>> + MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
>> + MIPSDSP_SPLIT32_16(rt, rth, rtl); \
>> + \
>> + temph = mipsdsp_##func(rsh, rth, env); \
>> + templ = mipsdsp_##func(rsl, rtl, env); \
>> + \
>> + return MIPSDSP_RETURN32_16(temph, templ); \
>> +}
>> +
>> +
>> +ARITH_PH_ENV(addq, add_i16);
>> +ARITH_PH_ENV(addq_s, sat_add_i16);
>> +ARITH_PH_ENV(addu, add_u16);
>> +ARITH_PH_ENV(addu_s, sat_add_u16);
>> +
>> +ARITH_PH(addqh, rshift1_add_q16);
>> +ARITH_PH(addqh_r, rrshift1_add_q16);
>> +
>> +ARITH_PH_ENV(subq, sub_i16);
>> +ARITH_PH_ENV(subq_s, sat16_sub);
>> +ARITH_PH_ENV(subu, sub_u16_u16);
>> +ARITH_PH_ENV(subu_s, satu16_sub_u16_u16);
>> +
>> +ARITH_PH(subqh, rshift1_sub_q16);
>> +ARITH_PH(subqh_r, rrshift1_sub_q16);
>> +
>> +#undef ARITH_PH
>> +#undef ARITH_PH_ENV
>> +
>> +#ifdef TARGET_MIPS64
>> +#define ARITH_QH_ENV(name, func) \
>> +target_ulong helper_##name##_qh(target_ulong rs, target_ulong rt, \
>> + CPUMIPSState *env) \
>> +{ \
>> + uint16_t rs3, rs2, rs1, rs0; \
>> + uint16_t rt3, rt2, rt1, rt0; \
>> + uint16_t tempD, tempC, tempB, tempA; \
>> + \
>> + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
>> + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
>> + \
>> + tempD = mipsdsp_##func(rs3, rt3, env); \
>> + tempC = mipsdsp_##func(rs2, rt2, env); \
>> + tempB = mipsdsp_##func(rs1, rt1, env); \
>> + tempA = mipsdsp_##func(rs0, rt0, env); \
>> + \
>> + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
>> +}
>> +
>> +ARITH_QH_ENV(addq, add_i16);
>> +ARITH_QH_ENV(addq_s, sat_add_i16);
>> +ARITH_QH_ENV(addu, add_u16);
>> +ARITH_QH_ENV(addu_s, sat_add_u16);
>> +
>> +ARITH_QH_ENV(subq, sub_i16);
>> +ARITH_QH_ENV(subq_s, sat16_sub);
>> +ARITH_QH_ENV(subu, sub_u16_u16);
>> +ARITH_QH_ENV(subu_s, satu16_sub_u16_u16);
>> +
>> +#undef ARITH_QH_ENV
>> +
>> +#endif
>> +
>> +#define ARITH_W(name, func) \
>> +target_ulong helper_##name##_w(target_ulong rs, target_ulong rt) \
>> +{ \
>> + uint32_t rd; \
>> + rd = mipsdsp_##func(rs, rt); \
>> + return MIPSDSP_RETURN32(rd); \
>> +}
>> +
>> +#define ARITH_W_ENV(name, func) \
>> +target_ulong helper_##name##_w(target_ulong rs, target_ulong rt, \
>> + CPUMIPSState *env) \
>> +{ \
>> + uint32_t rd; \
>> + rd = mipsdsp_##func(rs, rt, env); \
>> + return MIPSDSP_RETURN32(rd); \
>> +}
>> +
>> +ARITH_W_ENV(addq_s, sat_add_i32);
>> +
>> +ARITH_W(addqh, rshift1_add_q32);
>> +ARITH_W(addqh_r, rrshift1_add_q32);
>> +
>> +ARITH_W_ENV(subq_s, sat32_sub);
>> +
>> +ARITH_W(subqh, rshift1_sub_q32);
>> +ARITH_W(subqh_r, rrshift1_sub_q32);
>> +
>> +#undef ARITH_W
>> +#undef ARITH_W_ENV
>> +
>> +target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env)
>> +{
>> + uint32_t rd;
>> +
>> + rd = mipsdsp_sat_abs32(rt, env);
>> +
>> + return (target_ulong)rd;
>> +}
>> +
>> +
>> +#if defined(TARGET_MIPS64)
>> +
>> +#define ARITH_PW_ENV(name, func) \
>> +target_ulong helper_##name##_pw(target_ulong rs, target_ulong rt, \
>> + CPUMIPSState *env) \
>> +{ \
>> + uint32_t rs1, rs0; \
>> + uint32_t rt1, rt0; \
>> + uint32_t tempB, tempA; \
>> + \
>> + MIPSDSP_SPLIT64_32(rs, rs1, rs0); \
>> + MIPSDSP_SPLIT64_32(rt, rt1, rt0); \
>> + \
>> + tempB = mipsdsp_##func(rs1, rt1, env); \
>> + tempA = mipsdsp_##func(rs0, rt0, env); \
>> + \
>> + return MIPSDSP_RETURN64_32(tempB, tempA); \
>> +}
>> +
>> +ARITH_PW_ENV(addq, add_i32);
>> +ARITH_PW_ENV(addq_s, sat_add_i32);
>> +ARITH_PW_ENV(subq, sub32);
>> +ARITH_PW_ENV(subq_s, sat32_sub);
>> +
>> +#undef ARITH_PW_ENV
>> +
>> +#endif
>> +
>> +#define ARITH_QB(name, func) \
>> +target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
>> +{ \
>> + uint8_t rs0, rs1, rs2, rs3; \
>> + uint8_t rt0, rt1, rt2, rt3; \
>> + uint8_t temp0, temp1, temp2, temp3; \
>> + \
>> + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
>> + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
>> + \
>> + temp0 = mipsdsp_##func(rs0, rt0); \
>> + temp1 = mipsdsp_##func(rs1, rt1); \
>> + temp2 = mipsdsp_##func(rs2, rt2); \
>> + temp3 = mipsdsp_##func(rs3, rt3); \
>> + \
>> + return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \
>> +}
>> +
>> +#define ARITH_QB_ENV(name, func) \
>> +target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt, \
>> + CPUMIPSState *env) \
>> +{ \
>> + uint8_t rs0, rs1, rs2, rs3; \
>> + uint8_t rt0, rt1, rt2, rt3; \
>> + uint8_t temp0, temp1, temp2, temp3; \
>> + \
>> + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
>> + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
>> + \
>> + temp0 = mipsdsp_##func(rs0, rt0, env); \
>> + temp1 = mipsdsp_##func(rs1, rt1, env); \
>> + temp2 = mipsdsp_##func(rs2, rt2, env); \
>> + temp3 = mipsdsp_##func(rs3, rt3, env); \
>> + \
>> + return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \
>> +}
>> +
>> +ARITH_QB(adduh, rshift1_add_u8);
>> +ARITH_QB(adduh_r, rrshift1_add_u8);
>> +
>> +ARITH_QB_ENV(addu, add_u8);
>> +ARITH_QB_ENV(addu_s, sat_add_u8);
>> +
>> +#undef ADDU_QB
>> +#undef ADDU_QB_ENV
>> +
>> +#if defined(TARGET_MIPS64)
>> +#define ARITH_OB(name, func) \
>> +target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt) \
>> +{ \
>> + int i; \
>> + uint8_t rs_t[8], rt_t[8]; \
>> + uint8_t temp[8]; \
>> + uint64_t result; \
>> + \
>> + result = 0; \
>> + \
>> + for (i = 0; i < 8; i++) { \
>> + rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \
>> + rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
>> + temp[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \
>> + result |= (uint64_t)temp[i] << (8 * i); \
>> + } \
>> + \
>> + return result; \
>> +}
>> +
>> +#define ARITH_OB_ENV(name, func) \
>> +target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt, \
>> + CPUMIPSState *env) \
>> +{ \
>> + int i; \
>> + uint8_t rs_t[8], rt_t[8]; \
>> + uint8_t temp[8]; \
>> + uint64_t result; \
>> + \
>> + result = 0; \
>> + \
>> + for (i = 0; i < 8; i++) { \
>> + rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \
>> + rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \
>> + temp[i] = mipsdsp_##func(rs_t[i], rt_t[i], env); \
>> + result |= (uint64_t)temp[i] << (8 * i); \
>> + } \
>> + \
>> + return result; \
>> +}
>> +
>> +ARITH_OB_ENV(addu, add_u8);
>> +ARITH_OB_ENV(addu_s, sat_add_u8);
>> +
>> +ARITH_OB(adduh, rshift1_add_u8);
>> +ARITH_OB(adduh_r, rrshift1_add_u8);
>> +
>> +ARITH_OB_ENV(subu, sub_u8);
>> +ARITH_OB_ENV(subu_s, satu8_sub);
>> +
>> +ARITH_OB(subuh, rshift1_sub_u8);
>> +ARITH_OB(subuh_r, rrshift1_sub_u8);
>> +
>> +#undef ARITH_OB
>> +#undef ARITH_OB_ENV
>> +
>> +#endif
>> +
>> +#define SUBU_QB(name, func) \
>> +target_ulong helper_##name##_qb(target_ulong rs, \
>> + target_ulong rt, \
>> + CPUMIPSState *env) \
>> +{ \
>> + uint8_t rs3, rs2, rs1, rs0; \
>> + uint8_t rt3, rt2, rt1, rt0; \
>> + uint8_t tempD, tempC, tempB, tempA; \
>> + \
>> + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
>> + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
>> + \
>> + tempD = mipsdsp_##func(rs3, rt3, env); \
>> + tempC = mipsdsp_##func(rs2, rt2, env); \
>> + tempB = mipsdsp_##func(rs1, rt1, env); \
>> + tempA = mipsdsp_##func(rs0, rt0, env); \
>> + \
>> + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
>> +}
>> +
>> +SUBU_QB(subu, sub_u8);
>> +SUBU_QB(subu_s, satu8_sub);
>> +
>> +#undef SUBU_QB
>> +
>> +#define SUBUH_QB(name, var) \
>> +target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
>> +{ \
>> + uint8_t rs3, rs2, rs1, rs0; \
>> + uint8_t rt3, rt2, rt1, rt0; \
>> + uint8_t tempD, tempC, tempB, tempA; \
>> + \
>> + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \
>> + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
>> + \
>> + tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1; \
>> + tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \
>> + tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1; \
>> + tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \
>> + \
>> + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
>> +}
>> +
>> +SUBUH_QB(subuh, 0);
>> +SUBUH_QB(subuh_r, 1);
>> +
>> +#undef SUBUH_QB
>> +
>> +target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState
>> *env)
>> +{
>> + uint64_t temp, tempRs, tempRt;
>> + int32_t flag;
>> +
>> + tempRs = (uint64_t)rs & MIPSDSP_LLO;
>> + tempRt = (uint64_t)rt & MIPSDSP_LLO;
>> +
>> + temp = tempRs + tempRt;
>> + flag = (temp & 0x0100000000ull) >> 32;
>> + set_DSPControl_carryflag(flag, env);
>> +
>> + return (target_long)(int32_t)(temp & MIPSDSP_LLO);
>> +}
>> +
>> +target_ulong helper_addwc(target_ulong rs, target_ulong rt, CPUMIPSState
>> *env)
>> +{
>> + uint32_t rd;
>> + int32_t temp32, temp31;
>> + int64_t tempL;
>> +
>> + tempL = (int32_t)rs + (int32_t)rt + get_DSPControl_carryflag(env);
>> + temp31 = (tempL >> 31) & 0x01;
>> + temp32 = (tempL >> 32) & 0x01;
>> +
>> + if (temp31 != temp32) {
>> + set_DSPControl_overflow_flag(1, 20, env);
>> + }
>> +
>> + rd = tempL & MIPSDSP_LLO;
>> +
>> + return (target_long)(int32_t)rd;
>> +}
>> +
>> +target_ulong helper_modsub(target_ulong rs, target_ulong rt)
>> +{
>> + int32_t decr;
>> + uint16_t lastindex;
>> + target_ulong rd;
>> +
>> + decr = rt & MIPSDSP_Q0;
>> + lastindex = (rt >> 8) & MIPSDSP_LO;
>> +
>> + if ((rs & MIPSDSP_LLO) == 0x00000000) {
>> + rd = (target_ulong)lastindex;
>> + } else {
>> + rd = rs - decr;
>> + }
>> +
>> + return rd;
>> +}
>> +
>> +target_ulong helper_raddu_w_qb(target_ulong rs)
>> +{
>> + uint8_t rs3, rs2, rs1, rs0;
>> + uint16_t temp;
>> +
>> + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0);
>> +
>> + temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0;
>> +
>> + return (target_ulong)temp;
>> +}
>> +
>> +#if defined(TARGET_MIPS64)
>> +target_ulong helper_raddu_l_ob(target_ulong rs)
>> +{
>> + int i;
>> + uint16_t rs_t[8];
>> + uint64_t temp;
>> +
>> + temp = 0;
>> +
>> + for (i = 0; i < 8; i++) {
>> + rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0;
>> + temp += (uint64_t)rs_t[i];
>> + }
>> +
>> + return temp;
>> +}
>> +#endif
>> +
>> +target_ulong helper_absq_s_qb(target_ulong rt, CPUMIPSState *env)
>> +{
>> + uint8_t tempD, tempC, tempB, tempA;
>> +
>> + MIPSDSP_SPLIT32_8(rt, tempD, tempC, tempB, tempA);
>> +
>> + tempD = mipsdsp_sat_abs8(tempD, env);
>> + tempC = mipsdsp_sat_abs8(tempC, env);
>> + tempB = mipsdsp_sat_abs8(tempB, env);
>> + tempA = mipsdsp_sat_abs8(tempA, env);
>> +
>> + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
>> +}
>> +
>> +target_ulong helper_absq_s_ph(target_ulong rt, CPUMIPSState *env)
>> +{
>> + uint16_t tempB, tempA;
>> +
>> + MIPSDSP_SPLIT32_16(rt, tempB, tempA);
>> +
>> + tempB = mipsdsp_sat_abs16 (tempB, env);
>> + tempA = mipsdsp_sat_abs16 (tempA, env);
>> +
>> + return MIPSDSP_RETURN32_16(tempB, tempA);
>> +}
>> +
>> +#if defined(TARGET_MIPS64)
>> +target_ulong helper_absq_s_ob(target_ulong rt, CPUMIPSState *env)
>> +{
>> + int i;
>> + int8_t temp[8];
>> + uint64_t result;
>> +
>> + for (i = 0; i < 8; i++) {
>> + temp[i] = (rt >> (8 * i)) & MIPSDSP_Q0;
>> + temp[i] = mipsdsp_sat_abs8(temp[i], env);
>> + }
>> +
>> + for (i = 0; i < 8; i++) {
>> + result = (uint64_t)(uint8_t)temp[i] << (8 * i);
>> + }
>> +
>> + return result;
>> +}
>> +
>> +target_ulong helper_absq_s_qh(target_ulong rt, CPUMIPSState *env)
>> +{
>> + int16_t tempD, tempC, tempB, tempA;
>> +
>> + MIPSDSP_SPLIT64_16(rt, tempD, tempC, tempB, tempA);
>> +
>> + tempD = mipsdsp_sat_abs16(tempD, env);
>> + tempC = mipsdsp_sat_abs16(tempC, env);
>> + tempB = mipsdsp_sat_abs16(tempB, env);
>> + tempA = mipsdsp_sat_abs16(tempA, env);
>> +
>> + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
>> +}
>> +
>> +target_ulong helper_absq_s_pw(target_ulong rt, CPUMIPSState *env)
>> +{
>> + int32_t tempB, tempA;
>> +
>> + MIPSDSP_SPLIT64_32(rt, tempB, tempA);
>> +
>> + tempB = mipsdsp_sat_abs32(tempB, env);
>> + tempA = mipsdsp_sat_abs32(tempA, env);
>> +
>> + return MIPSDSP_RETURN64_32(tempB, tempA);
>> +}
>> +#endif
>> +
>> +#define PRECR_QB_PH(name, a, b)\
>> +target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
>> +{ \
>> + uint8_t tempD, tempC, tempB, tempA; \
>> + \
>> + tempD = (rs >> a) & MIPSDSP_Q0; \
>> + tempC = (rs >> b) & MIPSDSP_Q0; \
>> + tempB = (rt >> a) & MIPSDSP_Q0; \
>> + tempA = (rt >> b) & MIPSDSP_Q0; \
>> + \
>> + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \
>> +}
>> +
>> +PRECR_QB_PH(precr, 16, 0);
>> +PRECR_QB_PH(precrq, 24, 8);
>> +
>> +#undef PRECR_QB_OH
>> +
>> +target_ulong helper_precr_sra_ph_w(uint32_t sa, target_ulong rs,
>> + target_ulong rt)
>> +{
>> + uint16_t tempB, tempA;
>> +
>> + tempB = ((int32_t)rt >> sa) & MIPSDSP_LO;
>> + tempA = ((int32_t)rs >> sa) & MIPSDSP_LO;
>> +
>> + return MIPSDSP_RETURN32_16(tempB, tempA);
>> +}
>> +
>> +target_ulong helper_precr_sra_r_ph_w(uint32_t sa,
>> + target_ulong rs, target_ulong rt)
>> +{
>> + uint64_t tempB, tempA;
>> +
>> + /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need
>> else. */
>> + if (sa == 0) {
>> + tempB = (rt & MIPSDSP_LO) << 1;
>> + tempA = (rs & MIPSDSP_LO) << 1;
>> + } else {
>> + tempB = ((int32_t)rt >> (sa - 1)) + 1;
>> + tempA = ((int32_t)rs >> (sa - 1)) + 1;
>> + }
>> + rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO);
>> +
>> + return (target_long)(int32_t)rt;
>> +}
>> +
>> +target_ulong helper_precrq_ph_w(target_ulong rs, target_ulong rt)
>> +{
>> + uint16_t tempB, tempA;
>> +
>> + tempB = (rs & MIPSDSP_HI) >> 16;
>> + tempA = (rt & MIPSDSP_HI) >> 16;
>> +
>> + return MIPSDSP_RETURN32_16(tempB, tempA);
>> +}
>> +
>> +target_ulong helper_precrq_rs_ph_w(target_ulong rs, target_ulong rt,
>> + CPUMIPSState *env)
>> +{
>> + uint16_t tempB, tempA;
>> +
>> + tempB = mipsdsp_trunc16_sat16_round(rs, env);
>> + tempA = mipsdsp_trunc16_sat16_round(rt, env);
>> +
>> + return MIPSDSP_RETURN32_16(tempB, tempA);
>> +}
>> +
>> +#if defined(TARGET_MIPS64)
>> +target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt)
>> +{
>> + uint8_t rs6, rs4, rs2, rs0;
>> + uint8_t rt6, rt4, rt2, rt0;
>> + uint64_t temp;
>> +
>> + rs6 = (rs >> 48) & MIPSDSP_Q0;
>> + rs4 = (rs >> 32) & MIPSDSP_Q0;
>> + rs2 = (rs >> 16) & MIPSDSP_Q0;
>> + rs0 = rs & MIPSDSP_Q0;
>> + rt6 = (rt >> 48) & MIPSDSP_Q0;
>> + rt4 = (rt >> 32) & MIPSDSP_Q0;
>> + rt2 = (rt >> 16) & MIPSDSP_Q0;
>> + rt0 = rt & MIPSDSP_Q0;
>> +
>> + temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
>> + ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
>> + ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
>> + ((uint64_t)rt2 << 8) | (uint64_t)rt0;
>> +
>> + return temp;
>> +}
>> +
>> +#define PRECR_QH_PW(name, var) \
>> +target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \
>> + uint32_t sa) \
>> +{ \
>> + uint16_t rs3, rs2, rs1, rs0; \
>> + uint16_t rt3, rt2, rt1, rt0; \
>> + uint16_t tempD, tempC, tempB, tempA; \
>> + \
>> + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \
>> + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
>> + \
>> + /* When sa = 0, we use rt2, rt0, rs2, rs0; \
>> + * when sa != 0, we use rt3, rt1, rs3, rs1. */ \
>> + if (sa == 0) { \
>> + tempD = rt2 << var; \
>> + tempC = rt0 << var; \
>> + tempB = rs2 << var; \
>> + tempA = rs0 << var; \
>> + } else { \
>> + tempD = (((int16_t)rt3 >> sa) + var) >> var; \
>> + tempC = (((int16_t)rt1 >> sa) + var) >> var; \
>> + tempB = (((int16_t)rs3 >> sa) + var) >> var; \
>> + tempA = (((int16_t)rs1 >> sa) + var) >> var; \
>> + } \
>> + \
>> + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
>> +}
>> +
>> +PRECR_QH_PW(sra, 0);
>> +PRECR_QH_PW(sra_r, 1);
>> +
>> +#undef PRECR_QH_PW
>> +
>> +target_ulong helper_precrq_ob_qh(target_ulong rs, target_ulong rt)
>> +{
>> + uint8_t rs6, rs4, rs2, rs0;
>> + uint8_t rt6, rt4, rt2, rt0;
>> + uint64_t temp;
>> +
>> + rs6 = (rs >> 56) & MIPSDSP_Q0;
>> + rs4 = (rs >> 40) & MIPSDSP_Q0;
>> + rs2 = (rs >> 24) & MIPSDSP_Q0;
>> + rs0 = (rs >> 8) & MIPSDSP_Q0;
>> + rt6 = (rt >> 56) & MIPSDSP_Q0;
>> + rt4 = (rt >> 40) & MIPSDSP_Q0;
>> + rt2 = (rt >> 24) & MIPSDSP_Q0;
>> + rt0 = (rt >> 8) & MIPSDSP_Q0;
>> +
>> + temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
>> + ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
>> + ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
>> + ((uint64_t)rt2 << 8) | (uint64_t)rt0;
>> +
>> + return temp;
>> +}
>> +
>> +target_ulong helper_precrq_qh_pw(target_ulong rs, target_ulong rt)
>> +{
>> + uint16_t tempD, tempC, tempB, tempA;
>> +
>> + tempD = (rs >> 48) & MIPSDSP_LO;
>> + tempC = (rs >> 16) & MIPSDSP_LO;
>> + tempB = (rt >> 48) & MIPSDSP_LO;
>> + tempA = (rt >> 16) & MIPSDSP_LO;
>> +
>> + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
>> +}
>> +
>> +target_ulong helper_precrq_rs_qh_pw(target_ulong rs, target_ulong rt,
>> + CPUMIPSState *env)
>> +{
>> + uint32_t rs2, rs0;
>> + uint32_t rt2, rt0;
>> + uint16_t tempD, tempC, tempB, tempA;
>> +
>> + rs2 = (rs >> 32) & MIPSDSP_LLO;
>> + rs0 = rs & MIPSDSP_LLO;
>> + rt2 = (rt >> 32) & MIPSDSP_LLO;
>> + rt0 = rt & MIPSDSP_LLO;
>> +
>> + tempD = mipsdsp_trunc16_sat16_round(rs2, env);
>> + tempC = mipsdsp_trunc16_sat16_round(rs0, env);
>> + tempB = mipsdsp_trunc16_sat16_round(rt2, env);
>> + tempA = mipsdsp_trunc16_sat16_round(rt0, env);
>> +
>> + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
>> +}
>> +
>> +target_ulong helper_precrq_pw_l(target_ulong rs, target_ulong rt)
>> +{
>> + uint32_t tempB, tempA;
>> +
>> + tempB = (rs >> 32) & MIPSDSP_LLO;
>> + tempA = (rt >> 32) & MIPSDSP_LLO;
>> +
>> + return MIPSDSP_RETURN64_32(tempB, tempA);
>> +}
>> +#endif
>> +
>> +target_ulong helper_precrqu_s_qb_ph(target_ulong rs, target_ulong rt,
>> + CPUMIPSState *env)
>> +{
>> + uint8_t tempD, tempC, tempB, tempA;
>> + uint16_t rsh, rsl, rth, rtl;
>> +
>> + rsh = (rs & MIPSDSP_HI) >> 16;
>> + rsl = rs & MIPSDSP_LO;
>> + rth = (rt & MIPSDSP_HI) >> 16;
>> + rtl = rt & MIPSDSP_LO;
>> +
>> + tempD = mipsdsp_sat8_reduce_precision(rsh, env);
>> + tempC = mipsdsp_sat8_reduce_precision(rsl, env);
>> + tempB = mipsdsp_sat8_reduce_precision(rth, env);
>> + tempA = mipsdsp_sat8_reduce_precision(rtl, env);
>> +
>> + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
>> +}
>> +
>> +#if defined(TARGET_MIPS64)
>> +target_ulong helper_precrqu_s_ob_qh(target_ulong rs, target_ulong rt,
>> + CPUMIPSState *env)
>> +{
>> + int i;
>> + uint16_t rs3, rs2, rs1, rs0;
>> + uint16_t rt3, rt2, rt1, rt0;
>> + uint8_t temp[8];
>> + uint64_t result;
>> +
>> + result = 0;
>> +
>> + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
>> + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
>> +
>> + temp[7] = mipsdsp_sat8_reduce_precision(rs3, env);
>> + temp[6] = mipsdsp_sat8_reduce_precision(rs2, env);
>> + temp[5] = mipsdsp_sat8_reduce_precision(rs1, env);
>> + temp[4] = mipsdsp_sat8_reduce_precision(rs0, env);
>> + temp[3] = mipsdsp_sat8_reduce_precision(rt3, env);
>> + temp[2] = mipsdsp_sat8_reduce_precision(rt2, env);
>> + temp[1] = mipsdsp_sat8_reduce_precision(rt1, env);
>> + temp[0] = mipsdsp_sat8_reduce_precision(rt0, env);
>> +
>> + for (i = 0; i < 8; i++) {
>> + result |= (uint64_t)temp[i] << (8 * i);
>> + }
>> +
>> + return result;
>> +}
>> +
>> +#define PRECEQ_PW(name, a, b) \
>> +target_ulong helper_preceq_pw_##name(target_ulong rt) \
>> +{ \
>> + uint16_t tempB, tempA; \
>> + uint32_t tempBI, tempAI; \
>> + \
>> + tempB = (rt >> a) & MIPSDSP_LO; \
>> + tempA = (rt >> b) & MIPSDSP_LO; \
>> + \
>> + tempBI = (uint32_t)tempB << 16; \
>> + tempAI = (uint32_t)tempA << 16; \
>> + \
>> + return MIPSDSP_RETURN64_32(tempBI, tempAI); \
>> +}
>> +
>> +PRECEQ_PW(qhl, 48, 32);
>> +PRECEQ_PW(qhr, 16, 0);
>> +PRECEQ_PW(qhla, 48, 16);
>> +PRECEQ_PW(qhra, 32, 0);
>> +
>> +#undef PRECEQ_PW
>> +
>> +#endif
>> +
>> +#define PRECEQU_PH(name, a, b) \
>> +target_ulong helper_precequ_ph_##name(target_ulong rt) \
>> +{ \
>> + uint16_t tempB, tempA; \
>> + \
>> + tempB = (rt >> a) & MIPSDSP_Q0; \
>> + tempA = (rt >> b) & MIPSDSP_Q0; \
>> + \
>> + tempB = tempB << 7; \
>> + tempA = tempA << 7; \
>> + \
>> + return MIPSDSP_RETURN32_16(tempB, tempA); \
>> +}
>> +
>> +PRECEQU_PH(qbl, 24, 16);
>> +PRECEQU_PH(qbr, 8, 0);
>> +PRECEQU_PH(qbla, 24, 8);
>> +PRECEQU_PH(qbra, 16, 0);
>> +
>> +#undef PRECEQU_PH
>> +
>> +#if defined(TARGET_MIPS64)
>> +#define PRECEQU_QH(name, a, b, c, d) \
>> +target_ulong helper_precequ_qh_##name(target_ulong rt) \
>> +{ \
>> + uint16_t tempD, tempC, tempB, tempA; \
>> + \
>> + tempD = (rt >> a) & MIPSDSP_Q0; \
>> + tempC = (rt >> b) & MIPSDSP_Q0; \
>> + tempB = (rt >> c) & MIPSDSP_Q0; \
>> + tempA = (rt >> d) & MIPSDSP_Q0; \
>> + \
>> + tempD = tempD << 7; \
>> + tempC = tempC << 7; \
>> + tempB = tempB << 7; \
>> + tempA = tempA << 7; \
>> + \
>> + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
>> +}
>> +
>> +PRECEQU_QH(obl, 56, 48, 40, 32);
>> +PRECEQU_QH(obr, 24, 16, 8, 0);
>> +PRECEQU_QH(obla, 56, 40, 24, 8);
>> +PRECEQU_QH(obra, 48, 32, 16, 0);
>> +
>> +#undef PRECEQU_QH
>> +
>> +#endif
>> +
>> +#define PRECEU_PH(name, a, b) \
>> +target_ulong helper_preceu_ph_##name(target_ulong rt) \
>> +{ \
>> + uint16_t tempB, tempA; \
>> + \
>> + tempB = (rt >> a) & MIPSDSP_Q0; \
>> + tempA = (rt >> b) & MIPSDSP_Q0; \
>> + \
>> + return MIPSDSP_RETURN32_16(tempB, tempA); \
>> +}
>> +
>> +PRECEU_PH(qbl, 24, 16);
>> +PRECEU_PH(qbr, 8, 0);
>> +PRECEU_PH(qbla, 24, 8);
>> +PRECEU_PH(qbra, 16, 0);
>> +
>> +#undef PRECEU_PH
>> +
>> +#if defined(TARGET_MIPS64)
>> +#define PRECEU_QH(name, a, b, c, d) \
>> +target_ulong helper_preceu_qh_##name(target_ulong rt) \
>> +{ \
>> + uint16_t tempD, tempC, tempB, tempA; \
>> + \
>> + tempD = (rt >> a) & MIPSDSP_Q0; \
>> + tempC = (rt >> b) & MIPSDSP_Q0; \
>> + tempB = (rt >> c) & MIPSDSP_Q0; \
>> + tempA = (rt >> d) & MIPSDSP_Q0; \
>> + \
>> + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \
>> +}
>> +
>> +PRECEU_QH(obl, 56, 48, 40, 32);
>> +PRECEU_QH(obr, 24, 16, 8, 0);
>> +PRECEU_QH(obla, 56, 40, 24, 8);
>> +PRECEU_QH(obra, 48, 32, 16, 0);
>> +
>> +#undef PRECEU_QH
>> +
>> +#endif
>> +
>> +#undef MIPSDSP_LHI
>> +#undef MIPSDSP_LLO
>> +#undef MIPSDSP_HI
>> +#undef MIPSDSP_LO
>> +#undef MIPSDSP_Q3
>> +#undef MIPSDSP_Q2
>> +#undef MIPSDSP_Q1
>> +#undef MIPSDSP_Q0
>> +
>> +#undef MIPSDSP_SPLIT32_8
>> +#undef MIPSDSP_SPLIT32_16
>> +
>> +#undef MIPSDSP_RETURN32
>> +#undef MIPSDSP_RETURN32_8
>> +#undef MIPSDSP_RETURN32_16
>> +
>> +#ifdef TARGET_MIPS64
>> +#undef MIPSDSP_SPLIT64_16
>> +#undef MIPSDSP_SPLIT64_32
>> +#undef MIPSDSP_RETURN64_16
>> +#undef MIPSDSP_RETURN64_32
>> +#endif
>> diff --git a/target-mips/helper.h b/target-mips/helper.h
>> index f35ed78..9201aae 100644
>> --- a/target-mips/helper.h
>> +++ b/target-mips/helper.h
>> @@ -362,4 +362,130 @@ DEF_HELPER_FLAGS_2(pasubub, TCG_CALL_CONST |
>> TCG_CALL_PURE, i64, i64, i64)
>> DEF_HELPER_FLAGS_1(biadd, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
>> DEF_HELPER_FLAGS_1(pmovmskb, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64)
>>
>> +/*** MIPS DSP ***/
>> +/* DSP Arithmetic Sub-class insns */
>> +DEF_HELPER_FLAGS_3(addq_ph, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addq_s_ph, 0, tl, tl, tl, env)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_3(addq_qh, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addq_s_qh, 0, tl, tl, tl, env)
>> +#endif
>> +DEF_HELPER_FLAGS_3(addq_s_w, 0, tl, tl, tl, env)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_3(addq_pw, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addq_s_pw, 0, tl, tl, tl, env)
>> +#endif
>> +DEF_HELPER_FLAGS_3(addu_qb, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addu_s_qb, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(addu_ph, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addu_s_ph, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_3(addu_ob, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addu_s_ob, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(adduh_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(adduh_r_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(addu_qh, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addu_s_qh, 0, tl, tl, tl, env)
>> +#endif
>> +DEF_HELPER_FLAGS_3(subq_ph, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(subq_s_ph, 0, tl, tl, tl, env)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_3(subq_qh, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(subq_s_qh, 0, tl, tl, tl, env)
>> +#endif
>> +DEF_HELPER_FLAGS_3(subq_s_w, 0, tl, tl, tl, env)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_3(subq_pw, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(subq_s_pw, 0, tl, tl, tl, env)
>> +#endif
>> +DEF_HELPER_FLAGS_3(subu_qb, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(subu_s_qb, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(subu_ph, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(subu_s_ph, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_3(subu_ob, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(subu_s_ob, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(subuh_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(subuh_r_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(subu_qh, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(subu_s_qh, 0, tl, tl, tl, env)
>> +#endif
>> +DEF_HELPER_FLAGS_3(addsc, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_3(addwc, 0, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(modsub, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_1(raddu_l_ob, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +#endif
>> +DEF_HELPER_FLAGS_2(absq_s_qb, 0, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(absq_s_ph, 0, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(absq_s_w, 0, tl, tl, env)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_2(absq_s_ob, 0, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(absq_s_qh, 0, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(absq_s_pw, 0, tl, tl, env)
>> +#endif
>> +DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_CONST | TCG_CALL_PURE,
>> + tl, i32, tl, tl)
>> +DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_CONST | TCG_CALL_PURE,
>> + tl, i32, tl, tl)
>> +DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, tl, tl, tl, env)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_2(precr_ob_qh, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(precr_sra_qh_pw,
>> + TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32)
>> +DEF_HELPER_FLAGS_3(precr_sra_r_qh_pw,
>> + TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, i32)
>> +DEF_HELPER_FLAGS_2(precrq_ob_qh, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_2(precrq_qh_pw, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +DEF_HELPER_FLAGS_3(precrq_rs_qh_pw,
>> + TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, env)
>> +DEF_HELPER_FLAGS_2(precrq_pw_l, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
>> +#endif
>> +DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, tl, tl, tl, env)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_3(precrqu_s_ob_qh,
>> + TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl, env)
>> +
>> +DEF_HELPER_FLAGS_1(preceq_pw_qhl, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceq_pw_qhr, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceq_pw_qhla, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceq_pw_qhra, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +#endif
>> +DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_1(precequ_qh_obl, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(precequ_qh_obr, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(precequ_qh_obla, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(precequ_qh_obra, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +#endif
>> +DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +#if defined(TARGET_MIPS64)
>> +DEF_HELPER_FLAGS_1(preceu_qh_obl, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceu_qh_obr, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl)
>> +#endif
>> +
>> #include "def-helper.h"
>> diff --git a/target-mips/translate.c b/target-mips/translate.c
>> index 7f08700..a686e72 100644
>> --- a/target-mips/translate.c
>> +++ b/target-mips/translate.c
>> @@ -316,6 +316,21 @@ enum {
>>
>> /* MIPS DSP Load */
>> OPC_LX_DSP = 0x0A | OPC_SPECIAL3,
>> + /* MIPS DSP Arithmetic */
>> + OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3,
>> +#if defined(TARGET_MIPS64)
>> + OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3,
>> +#endif
>> + OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3,
>> +#if defined(TARGET_MIPS64)
>> + OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3,
>> +#endif
>> + /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */
>> + /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */
>> + OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3,
>> +#if defined(TARGET_MIPS64)
>> + OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3,
>> +#endif
>> };
>>
>> /* BSHFL opcodes */
>> @@ -354,6 +369,144 @@ enum {
>> #endif
>> };
>>
>> +#define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>> +enum {
>> + /* MIPS DSP Arithmetic Sub-class */
>> + OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP,
>> + OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP,
>> + OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP,
>> + OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP,
>> + OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP,
>> +};
>> +
>> +#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E
>> +#define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>> +enum {
>> + /* MIPS DSP Arithmetic Sub-class */
>> + OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP,
>> + OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP,
>> +};
>> +
>> +#define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>> +enum {
>> + /* MIPS DSP Arithmetic Sub-class */
>> + OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP,
>> + OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP,
>> +};
>> +
>> +#define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>> +enum {
>> + /* MIPS DSP Arithmetic Sub-class */
>> + OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP,
>> + OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP,
>> + OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP,
>> + OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP,
>> + OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP,
>> + OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP,
>> + OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP,
>> +};
>> +
>> +#if defined(TARGET_MIPS64)
>> +#define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>> +enum {
>> + /* MIPS DSP Arithmetic Sub-class */
>> + OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP,
>> + OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP,
>> +};
>> +#endif
>> +
>> +#if defined(TARGET_MIPS64)
>> +#define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>> +enum {
>> + /* MIPS DSP Arithmetic Sub-class */
>> + OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP,
>> + OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP,
>> +};
>> +#endif
>> +
>> +#if defined(TARGET_MIPS64)
>> +#define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6)))
>> +enum {
>> + /* MIPS DSP Arithmetic Sub-class */
>> + OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP,
>> + OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP,
>> + OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP,
>> + OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP,
>> + OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP,
>> + OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP,
>> + OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP,
>> + OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP,
>> +};
>> +#endif
>> +
>> /* Coprocessor 0 (rs field) */
>> #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
>>
>> @@ -12282,6 +12435,512 @@ static void gen_mipsdsp_ld(CPUMIPSState *env,
>> DisasContext *ctx, uint32_t opc,
>> tcg_temp_free(t0);
>> }
>>
>> +static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
>> + int ret, int v1, int v2)
>> +{
>> + const char *opn = "mipsdsp arith";
>> + TCGv v1_t = tcg_temp_new();
>> + TCGv v2_t = tcg_temp_new();
>> +
>
> Same as in the previous patch. This can cause a temp leak.
>
>> + if (ret == 0) {
>> + /* Treat as NOP. */
>> + MIPS_DEBUG("NOP");
>> + return;
>> + }
>> +
>> + if (v1 == 0) {
>> + tcg_gen_movi_tl(v1_t, 0);
>> + } else {
>> + gen_load_gpr(v1_t, v1);
>> + }
>> +
>> + if (v2 == 0) {
>> + tcg_gen_movi_tl(v2_t, 0);
>> + } else {
>> + gen_load_gpr(v2_t, v2);
>> + }
>
> You don't need to check if v1 or v2 == 0, this is already done in
> gen_load_gpr().
Sorry I'm a little confused here, just remove the check code here is OK?
>
>> +
>> + switch (op1) {
>> + /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
>> + case OPC_MULT_G_2E:
>> + check_dspr2(ctx);
>> + switch (op2) {
>> + case OPC_ADDUH_QB:
>> + gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_ADDUH_R_QB:
>> + gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_ADDQH_PH:
>> + gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_ADDQH_R_PH:
>> + gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_ADDQH_W:
>> + gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_ADDQH_R_W:
>> + gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_SUBUH_QB:
>> + gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_SUBUH_R_QB:
>> + gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_SUBQH_PH:
>> + gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_SUBQH_R_PH:
>> + gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_SUBQH_W:
>> + gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_SUBQH_R_W:
>> + gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + }
>> + break;
>> + case OPC_ABSQ_S_PH_DSP:
>> + switch (op2) {
>> + case OPC_ABSQ_S_QB:
>> + check_dspr2(ctx);
>> + gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env);
>> + break;
>> + case OPC_ABSQ_S_PH:
>> + check_dsp(ctx);
>> + gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env);
>> + break;
>> + case OPC_ABSQ_S_W:
>> + check_dsp(ctx);
>> + gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env);
>> + break;
>> + case OPC_PRECEQ_W_PHL:
>> + {
>> + TCGv temp = tcg_temp_new();;
>> + check_dsp(ctx);
>> + tcg_gen_andi_tl(temp, v2_t, 0xFFFF0000);
>> + tcg_gen_ext32s_tl(cpu_gpr[ret], temp);
>
> Small optimization; you don't need the temp here, andi can directly
> write to cpu_gpr[ret].
>
>> + tcg_temp_free(temp);
>> + break;
>> + }
>> + case OPC_PRECEQ_W_PHR:
>> + {
>> + TCGv temp = tcg_temp_new();;
>> + check_dsp(ctx);
>> + tcg_gen_andi_tl(temp, v2_t, 0x0000FFFF);
>
> This is not needed due to the shift and the ext below.
>
>> + tcg_gen_shli_tl(temp, temp, 16);
>> + tcg_gen_ext32s_tl(cpu_gpr[ret], temp);
>> + tcg_temp_free(temp);
>> + break;
>> + }
>> + case OPC_PRECEQU_PH_QBL:
>> + check_dsp(ctx);
>> + gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQU_PH_QBR:
>> + check_dsp(ctx);
>> + gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQU_PH_QBLA:
>> + check_dsp(ctx);
>> + gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQU_PH_QBRA:
>> + check_dsp(ctx);
>> + gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_PH_QBL:
>> + check_dsp(ctx);
>> + gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_PH_QBR:
>> + check_dsp(ctx);
>> + gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_PH_QBLA:
>> + check_dsp(ctx);
>> + gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_PH_QBRA:
>> + check_dsp(ctx);
>> + gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t);
>> + break;
>> + }
>> + break;
>> + case OPC_ADDU_QB_DSP:
>> + switch (op2) {
>> + case OPC_ADDQ_PH:
>> + check_dsp(ctx);
>> + gen_helper_addq_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDQ_S_PH:
>> + check_dsp(ctx);
>> + gen_helper_addq_s_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDQ_S_W:
>> + check_dsp(ctx);
>> + gen_helper_addq_s_w(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_QB:
>> + check_dsp(ctx);
>> + gen_helper_addu_qb(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_S_QB:
>> + check_dsp(ctx);
>> + gen_helper_addu_s_qb(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_PH:
>> + check_dspr2(ctx);
>> + gen_helper_addu_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_S_PH:
>> + check_dspr2(ctx);
>> + gen_helper_addu_s_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBQ_PH:
>> + check_dsp(ctx);
>> + gen_helper_subq_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBQ_S_PH:
>> + check_dsp(ctx);
>> + gen_helper_subq_s_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBQ_S_W:
>> + check_dsp(ctx);
>> + gen_helper_subq_s_w(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_QB:
>> + check_dsp(ctx);
>> + gen_helper_subu_qb(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_S_QB:
>> + check_dsp(ctx);
>> + gen_helper_subu_s_qb(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_PH:
>> + check_dspr2(ctx);
>> + gen_helper_subu_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_S_PH:
>> + check_dspr2(ctx);
>> + gen_helper_subu_s_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDSC:
>> + check_dsp(ctx);
>> + gen_helper_addsc(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDWC:
>> + check_dsp(ctx);
>> + gen_helper_addwc(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_MODSUB:
>> + check_dsp(ctx);
>> + gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_RADDU_W_QB:
>> + check_dsp(ctx);
>> + gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t);
>> + break;
>> + }
>> + break;
>> + case OPC_CMPU_EQ_QB_DSP:
>> + switch (op2) {
>> + case OPC_PRECR_QB_PH:
>> + check_dspr2(ctx);
>> + gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_PRECRQ_QB_PH:
>> + check_dsp(ctx);
>> + gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_PRECR_SRA_PH_W:
>> + check_dspr2(ctx);
>> + {
>> + TCGv_i32 sa_t = tcg_const_i32(v2);
>> + gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t,
>> + v1_t, cpu_gpr[ret]);
>> + tcg_temp_free_i32(sa_t);
>> + break;
>> + }
>> + case OPC_PRECR_SRA_R_PH_W:
>> + check_dspr2(ctx);
>> + {
>> + TCGv_i32 sa_t = tcg_const_i32(v2);
>> + gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t,
>> + v1_t, cpu_gpr[ret]);
>> + tcg_temp_free_i32(sa_t);
>> + break;
>> + }
>> + case OPC_PRECRQ_PH_W:
>> + check_dsp(ctx);
>> + gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_PRECRQ_RS_PH_W:
>> + check_dsp(ctx);
>> + gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_PRECRQU_S_QB_PH:
>> + check_dsp(ctx);
>> + gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + }
>> + break;
>> +#ifdef TARGET_MIPS64
>> + case OPC_ABSQ_S_QH_DSP:
>> + switch (op2) {
>> + case OPC_PRECEQ_L_PWL:
>> + check_dsp(ctx);
>> + tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull);
>> + break;
>> + case OPC_PRECEQ_L_PWR:
>> + check_dsp(ctx);
>> + tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFFull);
>
> This is wrong. The instruction put the 32-bit lower bits in the 32-bit
> higher bits, so this should be a simple shift left by 32.
>
>> + break;
>> + case OPC_PRECEQ_PW_QHL:
>> + check_dsp(ctx);
>> + gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQ_PW_QHR:
>> + check_dsp(ctx);
>> + gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQ_PW_QHLA:
>> + check_dsp(ctx);
>> + gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQ_PW_QHRA:
>> + check_dsp(ctx);
>> + gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQU_QH_OBL:
>> + check_dsp(ctx);
>> + gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQU_QH_OBR:
>> + check_dsp(ctx);
>> + gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQU_QH_OBLA:
>> + check_dsp(ctx);
>> + gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEQU_QH_OBRA:
>> + check_dsp(ctx);
>> + gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_QH_OBL:
>> + check_dsp(ctx);
>> + gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_QH_OBR:
>> + check_dsp(ctx);
>> + gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_QH_OBLA:
>> + check_dsp(ctx);
>> + gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_PRECEU_QH_OBRA:
>> + check_dsp(ctx);
>> + gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t);
>> + break;
>> + case OPC_ABSQ_S_OB:
>> + check_dspr2(ctx);
>> + gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env);
>> + break;
>> + case OPC_ABSQ_S_PW:
>> + check_dsp(ctx);
>> + gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env);
>> + break;
>> + case OPC_ABSQ_S_QH:
>> + check_dsp(ctx);
>> + gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env);
>> + break;
>> + }
>> + break;
>> + case OPC_ADDU_OB_DSP:
>> + switch (op2) {
>> + case OPC_RADDU_L_OB:
>> + check_dsp(ctx);
>> + gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t);
>> + break;
>> + case OPC_SUBQ_PW:
>> + check_dsp(ctx);
>> + gen_helper_subq_pw(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBQ_S_PW:
>> + check_dsp(ctx);
>> + gen_helper_subq_s_pw(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBQ_QH:
>> + check_dsp(ctx);
>> + gen_helper_subq_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBQ_S_QH:
>> + check_dsp(ctx);
>> + gen_helper_subq_s_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_OB:
>> + check_dsp(ctx);
>> + gen_helper_subu_ob(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_S_OB:
>> + check_dsp(ctx);
>> + gen_helper_subu_s_ob(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_QH:
>> + check_dspr2(ctx);
>> + gen_helper_subu_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBU_S_QH:
>> + check_dspr2(ctx);
>> + gen_helper_subu_s_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_SUBUH_OB:
>> + check_dspr2(ctx);
>> + gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_SUBUH_R_OB:
>> + check_dspr2(ctx);
>> + gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_ADDQ_PW:
>> + check_dsp(ctx);
>> + gen_helper_addq_pw(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDQ_S_PW:
>> + check_dsp(ctx);
>> + gen_helper_addq_s_pw(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDQ_QH:
>> + check_dsp(ctx);
>> + gen_helper_addq_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDQ_S_QH:
>> + check_dsp(ctx);
>> + gen_helper_addq_s_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_OB:
>> + check_dsp(ctx);
>> + gen_helper_addu_ob(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_S_OB:
>> + check_dsp(ctx);
>> + gen_helper_addu_s_ob(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_QH:
>> + check_dspr2(ctx);
>> + gen_helper_addu_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_ADDU_S_QH:
>> + check_dspr2(ctx);
>> + gen_helper_addu_s_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>
> All the call to the helpers above are on two lines, while they can be on
> one line only, improving the readability.
>
>> + case OPC_ADDUH_OB:
>> + check_dspr2(ctx);
>> + gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_ADDUH_R_OB:
>> + check_dspr2(ctx);
>> + gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + }
>> + break;
>> + case OPC_CMPU_EQ_OB_DSP:
>> + switch (op2) {
>> + case OPC_PRECR_OB_QH:
>> + check_dspr2(ctx);
>> + gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_PRECR_SRA_QH_PW:
>> + check_dspr2(ctx);
>> + {
>> + TCGv_i32 ret_t = tcg_const_i32(ret);
>> + gen_helper_precr_sra_qh_pw(v2_t, v1_t,
>> + v2_t, ret_t);
>> + tcg_temp_free_i32(ret_t);
>> + break;
>> + }
>> + case OPC_PRECR_SRA_R_QH_PW:
>> + check_dspr2(ctx);
>> + {
>> + TCGv_i32 sa_v = tcg_const_i32(ret);
>> + gen_helper_precr_sra_r_qh_pw(v2_t, v1_t,
>> + v2_t, sa_v);
>> + tcg_temp_free_i32(sa_v);
>> + break;
>> + }
>> + case OPC_PRECRQ_OB_QH:
>> + check_dsp(ctx);
>> + gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_PRECRQ_PW_L:
>> + check_dsp(ctx);
>> + gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_PRECRQ_QH_PW:
>> + check_dsp(ctx);
>> + gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t);
>> + break;
>> + case OPC_PRECRQ_RS_QH_PW:
>> + check_dsp(ctx);
>> + gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + case OPC_PRECRQU_S_OB_QH:
>> + check_dsp(ctx);
>> + gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t,
>> + v2_t, cpu_env);
>> + break;
>> + }
>> + break;
>> +#endif
>> + }
>> +
>> + tcg_temp_free(v1_t);
>> + tcg_temp_free(v2_t);
>> +
>> + (void)opn; /* avoid a compiler warning */
>> + MIPS_DEBUG("%s", opn);
>> +}
>>
>> /* End MIPSDSP functions. */
>>
>> @@ -12636,10 +13295,37 @@ static void decode_opc (CPUMIPSState *env,
>> DisasContext *ctx, int *is_branch)
>> }
>> break;
>> case OPC_DIV_G_2E ... OPC_DIVU_G_2E:
>> - case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
>> case OPC_MOD_G_2E ... OPC_MODU_G_2E:
>> - check_insn(env, ctx, INSN_LOONGSON2E);
>> - gen_loongson_integer(ctx, op1, rd, rs, rt);
>> + case OPC_MULT_G_2E ... OPC_MULTU_G_2E:
>> + /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
>> + * the same mask and op1. */
>> + if ((env->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
>> + op2 = MASK_ADDUH_QB(ctx->opcode);
>> + switch (op2) {
>> + case OPC_ADDUH_QB:
>> + case OPC_ADDUH_R_QB:
>> + case OPC_ADDQH_PH:
>> + case OPC_ADDQH_R_PH:
>> + case OPC_ADDQH_W:
>> + case OPC_ADDQH_R_W:
>> + case OPC_SUBUH_QB:
>> + case OPC_SUBUH_R_QB:
>> + case OPC_SUBQH_PH:
>> + case OPC_SUBQH_R_PH:
>> + case OPC_SUBQH_W:
>> + case OPC_SUBQH_R_W:
>> + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
>> + break;
>> + default:
>> + MIPS_INVAL("MASK ADDUH.QB");
>> + generate_exception(ctx, EXCP_RI);
>> + break;
>> + }
>> + } else if (env->insn_flags & INSN_LOONGSON2E) {
>> + gen_loongson_integer(ctx, op1, rd, rs, rt);
>> + } else {
>> + generate_exception(ctx, EXCP_RI);
>> + }
>> break;
>> case OPC_LX_DSP:
>> op2 = MASK_LX(ctx->opcode);
>> @@ -12658,6 +13344,80 @@ static void decode_opc (CPUMIPSState *env,
>> DisasContext *ctx, int *is_branch)
>> break;
>> }
>> break;
>> + case OPC_ABSQ_S_PH_DSP:
>> + op2 = MASK_ABSQ_S_PH(ctx->opcode);
>> + switch (op2) {
>> + case OPC_ABSQ_S_QB:
>> + case OPC_ABSQ_S_PH:
>> + case OPC_ABSQ_S_W:
>> + case OPC_PRECEQ_W_PHL:
>> + case OPC_PRECEQ_W_PHR:
>> + case OPC_PRECEQU_PH_QBL:
>> + case OPC_PRECEQU_PH_QBR:
>> + case OPC_PRECEQU_PH_QBLA:
>> + case OPC_PRECEQU_PH_QBRA:
>> + case OPC_PRECEU_PH_QBL:
>> + case OPC_PRECEU_PH_QBR:
>> + case OPC_PRECEU_PH_QBLA:
>> + case OPC_PRECEU_PH_QBRA:
>> + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
>> + break;
>> + default:
>> + MIPS_INVAL("MASK ABSQ_S.PH");
>> + generate_exception(ctx, EXCP_RI);
>> + break;
>> + }
>> + break;
>> + case OPC_ADDU_QB_DSP:
>> + op2 = MASK_ADDU_QB(ctx->opcode);
>> + switch (op2) {
>> + case OPC_ADDQ_PH:
>> + case OPC_ADDQ_S_PH:
>> + case OPC_ADDQ_S_W:
>> + case OPC_ADDU_QB:
>> + case OPC_ADDU_S_QB:
>> + case OPC_ADDU_PH:
>> + case OPC_ADDU_S_PH:
>> + case OPC_SUBQ_PH:
>> + case OPC_SUBQ_S_PH:
>> + case OPC_SUBQ_S_W:
>> + case OPC_SUBU_QB:
>> + case OPC_SUBU_S_QB:
>> + case OPC_SUBU_PH:
>> + case OPC_SUBU_S_PH:
>> + case OPC_ADDSC:
>> + case OPC_ADDWC:
>> + case OPC_MODSUB:
>> + case OPC_RADDU_W_QB:
>> + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
>> + break;
>> + default: /* Invalid */
>> + MIPS_INVAL("MASK ADDU.QB");
>> + generate_exception(ctx, EXCP_RI);
>> + break;
>> +
>> + }
>> + break;
>> + case OPC_CMPU_EQ_QB_DSP:
>> + op2 = MASK_CMPU_EQ_QB(ctx->opcode);
>> + switch (op2) {
>> + case OPC_PRECR_SRA_PH_W:
>> + case OPC_PRECR_SRA_R_PH_W:
>> + gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
>> + break;
>> + case OPC_PRECR_QB_PH:
>> + case OPC_PRECRQ_QB_PH:
>> + case OPC_PRECRQ_PH_W:
>> + case OPC_PRECRQ_RS_PH_W:
>> + case OPC_PRECRQU_S_QB_PH:
>> + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
>> + break;
>> + default: /* Invalid */
>> + MIPS_INVAL("MASK CMPU.EQ.QB");
>> + generate_exception(ctx, EXCP_RI);
>> + break;
>> + }
>> + break;
>> #if defined(TARGET_MIPS64)
>> case OPC_DEXTM ... OPC_DEXT:
>> case OPC_DINSM ... OPC_DINS:
>> @@ -12677,6 +13437,88 @@ static void decode_opc (CPUMIPSState *env,
>> DisasContext *ctx, int *is_branch)
>> check_insn(env, ctx, INSN_LOONGSON2E);
>> gen_loongson_integer(ctx, op1, rd, rs, rt);
>> break;
>> + case OPC_ABSQ_S_QH_DSP:
>> + op2 = MASK_ABSQ_S_QH(ctx->opcode);
>> + switch (op2) {
>> + case OPC_PRECEQ_L_PWL:
>> + case OPC_PRECEQ_L_PWR:
>> + case OPC_PRECEQ_PW_QHL:
>> + case OPC_PRECEQ_PW_QHR:
>> + case OPC_PRECEQ_PW_QHLA:
>> + case OPC_PRECEQ_PW_QHRA:
>> + case OPC_PRECEQU_QH_OBL:
>> + case OPC_PRECEQU_QH_OBR:
>> + case OPC_PRECEQU_QH_OBLA:
>> + case OPC_PRECEQU_QH_OBRA:
>> + case OPC_PRECEU_QH_OBL:
>> + case OPC_PRECEU_QH_OBR:
>> + case OPC_PRECEU_QH_OBLA:
>> + case OPC_PRECEU_QH_OBRA:
>> + case OPC_ABSQ_S_OB:
>> + case OPC_ABSQ_S_PW:
>> + case OPC_ABSQ_S_QH:
>> + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
>> + break;
>> + default: /* Invalid */
>> + MIPS_INVAL("MASK ABSQ_S.QH");
>> + generate_exception(ctx, EXCP_RI);
>> + break;
>> + }
>> + break;
>> + case OPC_ADDU_OB_DSP:
>> + op2 = MASK_ADDU_OB(ctx->opcode);
>> + switch (op2) {
>> + case OPC_RADDU_L_OB:
>> + case OPC_SUBQ_PW:
>> + case OPC_SUBQ_S_PW:
>> + case OPC_SUBQ_QH:
>> + case OPC_SUBQ_S_QH:
>> + case OPC_SUBU_OB:
>> + case OPC_SUBU_S_OB:
>> + case OPC_SUBU_QH:
>> + case OPC_SUBU_S_QH:
>> + case OPC_SUBUH_OB:
>> + case OPC_SUBUH_R_OB:
>> + case OPC_ADDQ_PW:
>> + case OPC_ADDQ_S_PW:
>> + case OPC_ADDQ_QH:
>> + case OPC_ADDQ_S_QH:
>> + case OPC_ADDU_OB:
>> + case OPC_ADDU_S_OB:
>> + case OPC_ADDU_QH:
>> + case OPC_ADDU_S_QH:
>> + case OPC_ADDUH_OB:
>> + case OPC_ADDUH_R_OB:
>> + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
>> + break;
>> + default: /* Invalid */
>> + MIPS_INVAL("MASK ADDU.OB");
>> + generate_exception(ctx, EXCP_RI);
>> + break;
>> + }
>> + break;
>> + case OPC_CMPU_EQ_OB_DSP:
>> + op2 = MASK_CMPU_EQ_OB(ctx->opcode);
>> + switch (op2) {
>> + case OPC_PRECR_SRA_QH_PW:
>> + case OPC_PRECR_SRA_R_QH_PW:
>> + /* Return value is rt. */
>> + gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd);
>> + break;
>> + case OPC_PRECR_OB_QH:
>> + case OPC_PRECRQ_OB_QH:
>> + case OPC_PRECRQ_PW_L:
>> + case OPC_PRECRQ_QH_PW:
>> + case OPC_PRECRQ_RS_QH_PW:
>> + case OPC_PRECRQU_S_OB_QH:
>> + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt);
>> + break;
>> + default: /* Invalid */
>> + MIPS_INVAL("MASK CMPU_EQ.OB");
>> + generate_exception(ctx, EXCP_RI);
>> + break;
>> + }
>> + break;
>> #endif
>> default: /* Invalid */
>> MIPS_INVAL("special3");
>> --
>> 1.7.10.2 (Apple Git-33)
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> address@hidden http://www.aurel32.net
Regards,
Jia.
[Qemu-devel] [PATCH v11 11/14] target-mips: Add ASE DSP accumulator instructions, Jia Liu, 2012/10/15
[Qemu-devel] [PATCH v11 13/14] target-mips: Add ASE DSP testcases, Jia Liu, 2012/10/15
[Qemu-devel] [PATCH v11 10/14] target-mips: Add ASE DSP compare-pick instructions, Jia Liu, 2012/10/15
[Qemu-devel] [PATCH v11 12/14] target-mips: Add ASE DSP processors, Jia Liu, 2012/10/15