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[Qemu-devel] [Bug 1071149] [NEW] target-mips: special3 instruction dinsm
From: |
Nikita Kanunnikov |
Subject: |
[Qemu-devel] [Bug 1071149] [NEW] target-mips: special3 instruction dinsm translation error |
Date: |
Thu, 25 Oct 2012 06:31:06 -0000 |
Public bug reported:
Function decode_opc() in translate.c calls function gen_bitops(), which
has such prototype:
/* special3 bitfield operations */
static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
int rs, int lsb, int msb)
The code for DINSM instruction is:
case OPC_DINSM ... OPC_DINS:
check_insn(env, ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
But rd ≠ msb according to MIPS64R2 standard, rd = msb - 32.
** Affects: qemu
Importance: Undecided
Status: New
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https://bugs.launchpad.net/bugs/1071149
Title:
target-mips: special3 instruction dinsm translation error
Status in QEMU:
New
Bug description:
Function decode_opc() in translate.c calls function gen_bitops(),
which has such prototype:
/* special3 bitfield operations */
static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
int rs, int lsb, int msb)
The code for DINSM instruction is:
case OPC_DINSM ... OPC_DINS:
check_insn(env, ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
But rd ≠ msb according to MIPS64R2 standard, rd = msb - 32.
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