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[Qemu-devel] [PATCH 03/16] target-ppc: Extend FPU state for newer POWER
From: |
David Gibson |
Subject: |
[Qemu-devel] [PATCH 03/16] target-ppc: Extend FPU state for newer POWER CPUs |
Date: |
Tue, 30 Oct 2012 14:24:59 +1100 |
This patch adds some extra FPU state to CPUPPCState. Specifically,
fpscr is extended to a target_ulong bits, since some recent (64 bit)
CPUs now have more status bits than fit inside 32 bits. Also, we add
the 32 VSR registers present on CPUs with VSX (these extend the
standard FP regs, which together with the Altivec/VMX registers form a
64 x 128bit register file for VSX).
We don't actually support the instructions using these extra registers
in TCG yet, but we still need a place to store the state so we can
sync it with KVM and savevm/loadvm it. This patch updates the savevm
code to not fail on the extended state, but also does not actually
save it - that's a project for another patch.
Signed-off-by: David Gibson <address@hidden>
---
v2:
* Used target_ulong instead of uint64_t, since the extended state is used
only on ppc64 targets.
* Fixed the TCG mapping of fpscr to match the new type.
---
target-ppc/cpu.h | 4 +++-
target-ppc/machine.c | 8 ++++++--
target-ppc/translate.c | 29 ++++++++++++++++++-----------
3 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index e603d9f..380a8d2 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -963,7 +963,7 @@ struct CPUPPCState {
/* floating point registers */
float64 fpr[32];
/* floating point status and control register */
- uint32_t fpscr;
+ target_ulong fpscr;
/* Next instruction pointer */
target_ulong nip;
@@ -1014,6 +1014,8 @@ struct CPUPPCState {
/* Altivec registers */
ppc_avr_t avr[32];
uint32_t vscr;
+ /* VSX registers */
+ uint64_t vsr[32];
/* SPE registers */
uint64_t spe_acc;
uint32_t spe_fscr;
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 21ce757..5e7bc00 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -6,6 +6,7 @@ void cpu_save(QEMUFile *f, void *opaque)
{
CPUPPCState *env = (CPUPPCState *)opaque;
unsigned int i, j;
+ uint32_t fpscr;
for (i = 0; i < 32; i++)
qemu_put_betls(f, &env->gpr[i]);
@@ -30,7 +31,8 @@ void cpu_save(QEMUFile *f, void *opaque)
u.d = env->fpr[i];
qemu_put_be64(f, u.l);
}
- qemu_put_be32s(f, &env->fpscr);
+ fpscr = env->fpscr;
+ qemu_put_be32s(f, &fpscr);
qemu_put_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
qemu_put_betls(f, &env->asr);
@@ -90,6 +92,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
CPUPPCState *env = (CPUPPCState *)opaque;
unsigned int i, j;
target_ulong sdr1;
+ uint32_t fpscr;
for (i = 0; i < 32; i++)
qemu_get_betls(f, &env->gpr[i]);
@@ -114,7 +117,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
u.l = qemu_get_be64(f);
env->fpr[i] = u.d;
}
- qemu_get_be32s(f, &env->fpscr);
+ qemu_get_be32s(f, &fpscr);
+ env->fpscr = fpscr;
qemu_get_sbe32s(f, &env->access_type);
#if defined(TARGET_PPC64)
qemu_get_betls(f, &env->asr);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 1042268..56725e6 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -68,7 +68,7 @@ static TCGv cpu_cfar;
#endif
static TCGv cpu_xer;
static TCGv cpu_reserve;
-static TCGv_i32 cpu_fpscr;
+static TCGv cpu_fpscr;
static TCGv_i32 cpu_access_type;
#include "gen-icount.h"
@@ -163,8 +163,8 @@ void ppc_translate_init(void)
offsetof(CPUPPCState, reserve_addr),
"reserve_addr");
- cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUPPCState, fpscr), "fpscr");
+ cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUPPCState, fpscr), "fpscr");
cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUPPCState,
access_type), "access_type");
@@ -2302,6 +2302,7 @@ GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
/* mcrfs */
static void gen_mcrfs(DisasContext *ctx)
{
+ TCGv tmp = tcg_temp_new();
int bfa;
if (unlikely(!ctx->fpu_enabled)) {
@@ -2309,9 +2310,11 @@ static void gen_mcrfs(DisasContext *ctx)
return;
}
bfa = 4 * (7 - crfS(ctx->opcode));
- tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa);
+ tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
+ tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
+ tcg_temp_free(tmp);
tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
0xf);
- tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
+ tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
}
/* mffs */
@@ -2322,7 +2325,7 @@ static void gen_mffs(DisasContext *ctx)
return;
}
gen_reset_fpstatus();
- tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
+ tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
}
@@ -2346,7 +2349,8 @@ static void gen_mtfsb0(DisasContext *ctx)
tcg_temp_free_i32(t0);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
}
@@ -2371,7 +2375,8 @@ static void gen_mtfsb1(DisasContext *ctx)
tcg_temp_free_i32(t0);
}
if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a differed exception */
gen_helper_float_check_status(cpu_env);
@@ -2397,7 +2402,8 @@ static void gen_mtfsf(DisasContext *ctx)
gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
tcg_temp_free_i32(t0);
if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a differed exception */
gen_helper_float_check_status(cpu_env);
@@ -2425,7 +2431,8 @@ static void gen_mtfsfi(DisasContext *ctx)
tcg_temp_free_i64(t0);
tcg_temp_free_i32(t1);
if (unlikely(Rc(ctx->opcode) != 0)) {
- tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX);
+ tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
+ tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
}
/* We can raise a differed exception */
gen_helper_float_check_status(cpu_env);
@@ -9463,7 +9470,7 @@ void cpu_dump_state (CPUPPCState *env, FILE *f,
fprintf_function cpu_fprintf,
if ((i & (RFPL - 1)) == (RFPL - 1))
cpu_fprintf(f, "\n");
}
- cpu_fprintf(f, "FPSCR %08x\n", env->fpscr);
+ cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
#if !defined(CONFIG_USER_ONLY)
cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
" PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
--
1.7.10.4
- [Qemu-devel] [0/16] pseries and PPC pending patches, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 01/16] Revert "PPC: pseries: Remove hack for PIO window", David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 04/16] pseries: Clean up inconsistent variable name in xics.c, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 12/16] target-pcc: Convert ppcemb_tlb_t to use fixed 64-bit RPN, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 09/16] pseries: Allow RTAS tokens without a qemu handler, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 08/16] pseries: Return the token when we register an RTAS call, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 03/16] target-ppc: Extend FPU state for newer POWER CPUs,
David Gibson <=
- [Qemu-devel] [PATCH 16/16] pseries: Generate unique LIOBNs for PCI host bridges, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 05/16] pseries: Use #define for XICS base irq number, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 06/16] pseries: Cleanup duplications of ics_valid_irq() code, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 15/16] pseries: Fix bug in PCI MSI allocation, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 10/16] pseries: Add tracepoints to the XICS interrupt controller, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 02/16] target-ppc: Rework storage of VPA registration state, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 13/16] pseries: Implement PAPR NVRAM, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 07/16] pseries: Move XICS initialization before cpu initialization, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 11/16] pseries: Split xics irq configuration from state information, David Gibson, 2012/10/29
- [Qemu-devel] [PATCH 14/16] pseries: Update SLOF for NVRAM support, David Gibson, 2012/10/29