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Re: [Qemu-devel] [PATCH v11 07/14] target-mips: Add ASE DSP GPR based sh


From: Jia Liu
Subject: Re: [Qemu-devel] [PATCH v11 07/14] target-mips: Add ASE DSP GPR based shift instructions
Date: Tue, 30 Oct 2012 22:47:14 +0800

Hi Aurelien,

On Wed, Oct 17, 2012 at 7:23 AM, Aurelien Jarno <address@hidden> wrote:
> On Tue, Oct 16, 2012 at 12:39:11AM +0800, Jia Liu wrote:
>> +static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
>> +                              int ret, int v1, int v2)
>> +{
>> +    uint32_t op2;
>> +    const char *opn = "mipsdsp shift";
>> +    TCGv t0 = tcg_const_tl(v1);
>> +    TCGv v1_t = tcg_temp_new();
>> +    TCGv v2_t = tcg_temp_new();
>> +
>> +    if (ret == 0) {
>> +        /* Treat as NOP. */
>> +        MIPS_DEBUG("NOP");
>> +        return;
>> +    }
>> +
>> +    if (v1 == 0) {
>> +        tcg_gen_movi_tl(v1_t, 0);
>> +    } else {
>> +        gen_load_gpr(v1_t, v1);
>> +    }
>> +
>> +    if (v2 == 0) {
>> +        tcg_gen_movi_tl(v2_t, 0);
>> +    } else {
>> +        gen_load_gpr(v2_t, v2);
>> +    }
>
> Same comments as for the previous patch. In addition if v1 is a
> constant, gen_load_gpr() is likely to generate wrong code (if not a
> crash).
>

The ret/v1/v2 are all reg number, come from rs, rt or rd, so it can't
be a neg value.
Need I add a comment here, or change the variable name?

>
> --
> Aurelien Jarno                          GPG: 1024D/F1BCDB73
> address@hidden                 http://www.aurel32.net

Regards,
Jia.



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