qemu-devel
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major opcode


From: Johnson, Eric
Subject: Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major opcode
Date: Thu, 15 Nov 2012 02:34:31 +0000

Hi Chen,

Please only remove the POOL48A opcode.

The others are documented in the microMIPS64 Instruction Set manual ( 
http://www.mips.com/secure-download/index.dot?product_name=/auth/MD00087-2B-MIPS64BIS-AFP-03.51.pdf
 ).  See http://www.mips.com/products/architectures/mips64/ for other relavent 
docs.

Instead of removing them please surround the POOL32S, DADDIU32, SD32, and LD32 
opcodes with
#if defined(TARGET_MIPS64)

-Eric

> -----Original Message-----
> From: address@hidden [mailto:qemu-devel-
> address@hidden On Behalf Of ??? (Wei-Ren Chen)
> Sent: Wednesday, November 14, 2012 6:15 PM
> To: address@hidden; address@hidden
> Cc: address@hidden; Jia Liu; Aurelien Jarno
> Subject: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major
> opcode
> 
> Hi all,
> 
>   I check MIPS microMIPS manual [1], and found the major opcode might be
> wrong. I add a comment to explicitly indicate what manual I am refering
> to, and according that manual I remove some microMIPS32 major opcodes.
> Major opcode 0x1f is reserved, so I just remove it. As for others, like
> 0x16, 0x17, 0x36 and 0x37, they are for higher-order MIPS ISA level or
> new revision of this microMIPS architecture. Since they are not appear
> in the manual I refer to, I just remove them as well.
> 
>   Please review, thanks.
> 
> [1] http://www.mips.com/products/architectures/micromips/#specifications
> 
>     MIPS Architecture for Programmers Volume II-B:
>       The microMIPS32 Instruction Set (Revision 3.05)
> 
>     MD00582-2B-microMIPS-AFP-03.05.pdf
> 
> Signed-off-by: Chen Wei-Ren <address@hidden>
> ---
>  target-mips/translate.c |   16 ++++++++++------
>  1 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index f6fc0c2..b57da24 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10241,7 +10241,15 @@ static int decode_mips16_opc (CPUMIPSState *env,
> DisasContext *ctx,
> 
>  /* microMIPS extension to MIPS32 */
> 
> -/* microMIPS32 major opcodes */
> +/*
> + * microMIPS32 major opcodes
> + *
> + * MIPS Architecture for Programmers Volume II-B:
> + *   The microMIPS32 Instruction Set (Revision 3.05)
> + *
> + * Table 6.2 microMIPS32 Encoding of Major Opcode Field
> + *
> + */
> 
>  enum {
>      POOL32A = 0x00,
> @@ -10268,9 +10276,8 @@ enum {
>      POOL16D = 0x13,
>      ORI32 = 0x14,
>      POOL32F = 0x15,
> -    POOL32S = 0x16,
> -    DADDIU32 = 0x17,
> 
> +    /* 0x1f is reserved */
>      POOL32C = 0x18,
>      LWGP16 = 0x19,
>      LW16 = 0x1a,
> @@ -10278,7 +10285,6 @@ enum {
>      XORI32 = 0x1c,
>      JALS32 = 0x1d,
>      ADDIUPC = 0x1e,
> -    POOL48A = 0x1f,
> 
>      /* 0x20 is reserved */
>      RES_20 = 0x20,
> @@ -10307,8 +10313,6 @@ enum {
>      B16 = 0x33,
>      ANDI32 = 0x34,
>      J32 = 0x35,
> -    SD32 = 0x36,
> -    LD32 = 0x37,
> 
>      /* 0x38 and 0x39 are reserved */
>      RES_38 = 0x38,
> --
> 1.7.3.4


reply via email to

[Prev in Thread] Current Thread [Next in Thread]