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Re: [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved instructio
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved instruction exception on CPU without DSP |
Date: |
Fri, 16 Nov 2012 14:02:58 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121029 Thunderbird/16.0.2 |
On 11/16/2012 03:04 AM, Aurelien Jarno wrote:
> +static inline void check_dsp(CPUMIPSState *env, DisasContext *ctx)
> {
> if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
> - generate_exception(ctx, EXCP_DSPDIS);
> + if (env->insn_flags & ASE_DSP) {
> + generate_exception(ctx, EXCP_DSPDIS);
> + } else {
> + generate_exception(ctx, EXCP_RI);
> + }
Perhaps it would make more sense to copy env->insn_flags into
a new field in DisasContext at the start of translation, rather
than modify 300 instances to pass around a second pointer?
r~
- [Qemu-devel] [PATCH 0/7] target-mips: DSP ASE fixes and cleanup, Aurelien Jarno, 2012/11/16
- [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0, Aurelien Jarno, 2012/11/16
- [Qemu-devel] [PATCH 6/7] target-mips: use DSP unions for reduction add instructions, Aurelien Jarno, 2012/11/16
- [Qemu-devel] [PATCH 3/7] target-mips: add unions to access DSP elements, Aurelien Jarno, 2012/11/16
- [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved instruction exception on CPU without DSP, Aurelien Jarno, 2012/11/16
- Re: [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved instruction exception on CPU without DSP,
Richard Henderson <=
- [Qemu-devel] [PATCH 5/7] target-mips: use DSP unions for unary DSP operators, Aurelien Jarno, 2012/11/16
- [Qemu-devel] [PATCH 4/7] target-mips: use DSP unions for binary DSP operators, Aurelien Jarno, 2012/11/16
- [Qemu-devel] [PATCH 7/7] target-mips: implement DSP (d)append sub-class with TCG, Aurelien Jarno, 2012/11/16