Re: [Qemu-devel] Interrupt controller updates

[Benjamin Herrenschmidt]

On Thu, 2012-11-22 at 11:25 +0100, Paolo Bonzini wrote:
> > Again, from memory, you were volunteered to do the initial x86
> change so
> > we could piggy back on it :-) Or do I remember wrong ?
> 
> Please suggest an API, then we can work out the x86 changes.  I can
> volunteer myself, but I wasn't in the BOF so I need something more
> concrete. 

Oh it's simple enough initially, just move the ioctl call from generic
kvm init to machine init. The problem is then to add an argument, since
that essentially means changing the ioctl number, but we need that for
all archs where the interrupt subsystem can be fundamentally different
based on the platform.

Basically, what was discussed in the BOF was that we split the init:

 * The existing ioctl moves to early machine init (before VCPUs) and
gets that argument to define the type of interrupt subsystem to use. It
causes powerpc to instanciate ICPs per VCPUs for example. On archs that
don't have a per-vcpu structure (equivalent of local APIC or ICP), all
it does is enable subsequent irq related ioctls to work (it's just an
"enable" flag).

 * A new ioctl is used to actually instanciate external interrupt
controllers (GIC on ARM, ICS for ppc/pseries, MPIC for ppc/mpic, ...).
This is used later by the PIC code itself when the former ioctl has
enabled "in kernel PIC"

 * A new ioctl is used for platforms that need to be able to adjust the
base address of a PIC (arm/GIC, ppc/mpic)

We have other things to look at (mostly along the MSI routing calls in
qemu that need to be changed to be PCI bridge hooks populated by the
platform) but that's the starting point.

Cheers,
Ben.