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Re: [Qemu-devel] MIPS exception number limits?


From: Johnson, Eric
Subject: Re: [Qemu-devel] MIPS exception number limits?
Date: Tue, 27 Nov 2012 05:25:32 +0000

> -----Original Message-----
> From: address@hidden [mailto:qemu-devel-
> address@hidden On Behalf Of ??? (Wei-Ren Chen)
> Sent: Thursday, November 22, 2012 11:34 AM
> To: address@hidden
> Subject: [Qemu-devel] MIPS exception number limits?
> 
> Hi all,
> 
>   Wondering why MIPS limits exception number less then 0x100,
> you can see such example in function do_raise_exception_err
> (target-mips/op_helper.c). See below,
> 
> static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
>                                                         ...
> {
>   ...
> 
> #if 1
>     if (exception < 0x100)
>         qemu_log("%s: %d %d\n", __func__, exception, error_code);
> #endif
> 
>   ...
> }
> 
>   Anyone can help confirm this, stated in what spec? Also, do we
> need "#if 1 .. #endif"? Thanks for help. =]
> 
> Regards,
> chenwj
> 
> --
> Wei-Ren Chen (陳韋任)
> Computer Systems Lab, Institute of Information Science,
> Academia Sinica, Taiwan (R.O.C.)
> Tel:886-2-2788-3799 #1667
> Homepage: http://people.cs.nctu.edu.tw/~chenwj

The 0x100 is an arbitrary value known to be larger than the maximum possible 
CP0.Cause.ExcCode value.

From target-mips/cpu.h:
/* Dummy exception for conditional stores.  */
#define EXCP_SC 0x100

From target-mips/translate.c:
    gen_helper_0e0i(raise_exception, EXCP_SC); \

It can be seen the only use of EXCP_SC is for the macro OP_ST_ATOMIC when 
CONFIG_USER_ONLY is defined.

So basically the SC and SCD instructions for user-mode QEMU are implemented 
with a "dummy" exception.  Since it is not a real exception, it is not reported 
in the QEMU log file as an exception.

-Eric

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