Re: [Qemu-devel] [PATCH] target-mips: Fix incorrect shift for SHILO and SHILOV

[Jovanovic, Petar]

> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index e7949c2..f8a7a9f 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -3814,17 +3814,17 @@ void helper_shilo(target_ulong ac, target_ulong rs, 
> CPUMIPSState *env)
>
>      rs5_0 = rs & 0x3F;
>      rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
> -    rs5_0 = MIPSDSP_ABS(rs5_0);
> +
> +    if (rs5_0 == 0)
> +        return;

> The check should be moved to translation time so that the call to this
> helper is not generated at all.

This case is not likely so generation of unnecessary call is unlikely too.
Let me know what you think.

I will add the missing braces and I can also get rid of
MIPSDSP_ABS(rs5_0).

Petar